Metallization
Metallization — depositing metal layers on a chip to create the wiring that connects billions of transistors, forming the interconnect stack that can be 10-15 layers deep.
Evolution of Metals
| Generation | Metal | Resistivity | Notes |
|---|---|---|---|
| Pre-1997 | Aluminum (Al) | 2.7 μΩ·cm | Easy to etch, but electromigration issues |
| 1997+ | Copper (Cu) | 1.7 μΩ·cm | 40% lower resistance, damascene process required |
| 2020s+ | Cobalt (Co), Ruthenium (Ru) | ~6 μΩ·cm (bulk) | Better at narrow widths where Cu resistance rises |
Copper Dual Damascene Process
1. Deposit dielectric layer
2. Pattern and etch trench and via
3. Deposit barrier (TaN/Ta) to prevent Cu diffusion into silicon
4. Deposit Cu seed layer (PVD)
5. Electroplate Cu to fill trench
6. CMP to remove excess Cu and planarize
Interconnect Stack
- Local (M1-M2): Thin, tight-pitch wires connecting nearby transistors
- Intermediate (M3-M6): Medium wires for block-level routing
- Global (M7+): Thick, wide wires for power, ground, and long-distance signals
Scaling Challenge
- As wires narrow, resistance increases (electron scattering off sidewalls)
- Wire RC delay now dominates over transistor delay at advanced nodes
Metallization connects the transistors into a functioning circuit — the interconnect challenge is now harder than the transistor challenge itself.