Nano-TSV

Nano-TSVs are the sub-micron through-silicon vias that carry power from the back of a thinned wafer to the buried power rails sitting just beneath the transistors. They are what makes backside power delivery an electrical reality rather than a layout idea, and they are a different device from the package-level TSV that shares the name.

Two orders of magnitude apart

Interposer TSVNano-TSV
Diameter5–10 µmdemonstrated down to 20 nm bottom diameter; scheme-dependent
Depth50–100 µmseveral hundred nanometres; 320 nm demonstrated in one BPR flow
Aspect ratio10–20:1variable; controlled by thinning and integration scheme
Pitch40–100 µmsub-micron
Lands onpackage RDLburied power rail
Keep-out zone3–10 µmsmall
Limiting physicsmechanical stressresistance

The aspect ratio is similar; everything else differs by two orders of magnitude. The consequence is that the two are limited by opposite mechanisms. An interposer TSV is constrained by the stress it projects into surrounding silicon, since the keep-out zone scales with via radius and sterilises area quadratically. Shrink the via to a few hundred nanometres and that penalty largely evaporates — but resistance, which scales as

$$ R_{\text{nTSV}} = \frac{4\rho\,h}{\pi d^{2}} $$

becomes brutal. Halving the diameter quadruples resistance, and a nano-TSV is already two orders of magnitude narrower than its package-level cousin. The engineering fight in BSPDN is therefore conductance, not mechanics.

The buried power rail it lands on

A nano-TSV terminates on a buried power rail: a trench cut into the shallow-trench isolation below the device layer and filled with a refractory metal before the transistors are finished. Tungsten and ruthenium are the candidates, chosen because they survive the full subsequent thermal budget — copper does not, and would contaminate the device layer besides.

Burying the rail removes $V_{DD}$ and $V_{SS}$ from the cell's metal stack, which is what releases routing tracks and takes standard cells below 5T. But a buried rail is small, and a small refractory conductor has high resistance, so the rail can only be short: it must be re-fed from the backside network frequently. Nano-TSV pitch is therefore set by the acceptable IR drop along the rail between feed points, not by how densely vias could be patterned.

$$ \Delta V_{\text{rail}} = I \cdot R_{\square}\,\frac{L_{\text{seg}}}{W_{\text{rail}}} $$

The contact is usually the limit

Total path resistance from backside metal to device is the sum of three terms:

$$ R_{\text{total}} = R_{\text{bsm}} + R_{\text{nTSV}} + R_{c}, \qquad R_{c} = \frac{\rho_c}{A_c} $$

Backside metal is thick and wide, so $R_{\text{bsm}}$ is negligible — that is the entire point of the architecture. The via body contributes meaningfully. But the interface where the nano-TSV meets the buried rail has an area set by a via a few hundred nanometres across landing on a rail a few tens of nanometres wide, and with $R_c$ inversely proportional to that area, it typically dominates. This is why low-temperature silicide and ALD barrier metallurgy on the backside receive attention out of proportion to their apparent simplicity.

Nano-TSV and Buried Power Rail Integration via pitch set by IR drop along the rail, not by patterning limits signal nanosheet device layer buried power rail — W / Ru in STI trench L_seg nano-TSV thinned Si — etch-stop reveal backside power metal — thick, wide, low R R_c dominates nano-TSV lands on a rail tens of nm wide — tiny A_c Pitch trade more vias → lower ΔV_rail but each costs device area above

Process integration

The sequence is demanding because it happens to a finished wafer. The device wafer is bonded face-down to a carrier, ground and then etched to a few hundred nanometres, stopping on a buried etch-stop layer — usually a SiGe marker placed during epitaxy, since a timed grind cannot hold that tolerance. Vias are then patterned from the back, aligned to front-side features read through the remaining silicon, etched, lined by ALD barrier, and filled.

Every step is capped near 400 °C because the full BEOL already exists on the other face. Overlay is referenced through the substrate rather than to a surface mark, and the accuracy achievable there sets how small the via can be — a misregistered nano-TSV either misses its rail or shorts to an adjacent node. Neither is repairable.

Making a Nano-TSV — Turning a Finished Wafer Inside-Out bond the completed frontside, then thin the silicon to hundreds of nanometres align, etch, and fill the power connection from behind 1 · frontside devices + BPR buried rail in STI device wafer SiGe etch stop below devices 2 · bond face-down carrier wafer SiCN bond supports the thin device layer 3 · thin to etch stop grind · CMP · dry/wet etch soft-land on ~10 nm SiGe marker 4 · etch + fill from back through-Si alignment W or barrierless Mo fill the control loop is thickness → overlay → contact resistance thicker remaining Si longer via · higher R · harder etch overlay miss misses a ~30 nm rail or shorts its neighbour smaller bottom contact saves cell area but raises Rc ∝ 1/Ac Imec demonstration: 320 nm-deep nTSVs at 200 nm pitch; roadmap: 20 nm-bottom Mo vias at 120 nm pitch. These are demonstrated integration points, not universal product design rules.

The trade-off in one line

More vias mean lower rail IR drop but more device area consumed and more of the thermal path replaced by metal and bonding interfaces. Fewer vias mean a cleaner device layer and a worse power grid. Backside power delivery is, in the end, an optimisation over nano-TSV pitch, and every other parameter in the architecture is downstream of that choice.

Nano-TSV Scaling — Diameter Is Paid for Twice for fixed depth, both via-body resistance and contact resistance rise approximately as 1/d² 2050100200300500 nm 1×4×16×64×256× via or contact diameter → normalized resistance penalty ← Rvia = 4ρh / πd² Rc = ρc / Ac material can move the curve barrierless Mo preserves more conducting area but geometry still imposes the d⁻² penalty why the smallest via is not always best smaller d saves cell area and eases placement but raises voltage drop and local current density optimum pitch comes from the rail IR-drop budget The toll bridge is low-resistance contact at nanometre scale—etch profile, fill metal, overlay, and rail landing all compound.

Current demonstrated geometry

Nano-TSV dimensions are not one fixed aspect ratio. They depend on whether the connection is via-first, via-middle or via-last, circular or slit-shaped, and whether it lands on a buried rail or a device contact. Imec has demonstrated 320 nm-deep nTSVs landing on buried power rails at 200 nm pitch. Its 2025 roadmap also demonstrated barrierless molybdenum through-dielectric vias with a bottom diameter as small as 20 nm at 120 nm pitch. The latter requires extreme thinning precisely to keep aspect ratio and resistance manageable.

Barrierless fill matters because a liner consumes an increasing fraction of the conducting cross-section as diameter shrinks. Molybdenum can remove that geometrical tax relative to a lined tungsten or copper scheme, but it cannot repeal the $1/d^2$ resistance law. The design optimum remains a system trade among standard-cell area, overlay margin, via resistance, contact resistance and rail IR drop.

The toll bridge

The scarce capability is not simply printing a small hole. A manufacturable flow must bond the completed wafer, thin it with tens-of-nanometres total-thickness control, align through the remaining silicon, etch without damaging the landing rail, deposit a conformal liner or barrierless fill, and hold contact resistance across billions of vias. Each step changes the next one's margin. That coupled process window—and its yield data—is the economic moat.

References

  • Imec, “Backside power delivery options: a DTCO study” (2023).
  • Imec, “Backside power delivery” process-flow overview (2022–2023).
  • Imec, “A path to high-density front and backside wafer connectivity” (2025).
  • IEEE Transactions on Electron Devices, “Backside Power Delivery With Relaxed Overlay … and Molybdenum-Filled Slit Nano Through Silicon Vias” (2024).

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