Nanowire FET: wrap the gate all the way around the channel Gate-all-around gives the best electrostatics — stack the wires back to get the drive current 1 · More gated sides how much of the channel the gate touches planar 1 side FinFET 3 sides GAA wire all around tighter electrostatic control Wrapping the gate on every side lets it shut the channel completely: a steeper subthreshold slope and far less drain-induced leakage than a fin. Copper = gate · green = silicon channel. This is the device behind the “GAA” nanosheet node at 2nm-class logic. 2 · One wire is too thin stack channels to add drive width single wire low current stacked sheets 3× the width A lone nanowire has a tiny perimeter, so it carries little current. Stacking several sheets under one shared gate multiplies effective width in the same footprint — this is the nanosheet FET. Sheet width is tunable: wide for drive, narrow for low-power cells. 3 · How it’s built the Si / SiGe superlattice trick Grow a superlattice alternating Si and SiGe epitaxial layers — Si becomes the channels. Release the channels a selective etch removes the SiGe, leaving suspended Si wires/sheets. Wrap gate + inner spacer high-k/metal fills all around each sheet; spacers isolate it from S/D. Nanowire → nanosheet → CFET The wire was the lab prototype; wide sheets made it manufacturable (GAA). Next, CFET stacks nMOS over pMOS sheets to fold the cell in half. Gate-all-around Gate surrounds the channel on every side — the tightest control possible. Drive by stacking More sheets = more width = more current, with no extra floor area. The GAA lineage Nanowire → nanosheet is how logic moved past FinFET at 3/2nm. Nanowire FET
Nanowire FET is a Gate-All-Around (GAA) transistor with cylindrical (wire-shaped) silicon channels fully surrounded by the gate electrode. It offers the best electrostatic control of any transistor geometry.
Nanowire vs. Nanosheet
Nanowire: Circular/small cross-section (~5-10nm diameter). Best gate control but limited drive current per wire. Nanosheet: Wider rectangular cross-section (10-50nm wide). More drive current per sheet. Preferred by industry for production. Both are GAA: Gate wraps all four sides. Nanosheets are essentially wide nanowires. Fabrication
1. Grow alternating Si/SiGe superlattice stack.
Advantages
Superior electrostatic control: Near-ideal subthreshold slope (~62 mV/dec at room temp). Excellent short-channel effect suppression: DIBL < 30 mV/V. Low leakage: Gate fully controls the channel with no ungated surfaces. Challenges
Drive Current: Small cross-section limits current per wire. Must stack many wires (4-8) to get adequate drive. Variability: Small dimensional variations in wire diameter have large impact on threshold voltage. Parasitic Capacitance: Gate wrapping multiple wires in close proximity increases capacitance.