On Chip Interconnect Design
On-Chip Interconnect Design is the architecture and implementation of communication infrastructure connecting processors, memories, accelerators, and peripherals within an SoC, from simple shared buses to sophisticated Networks-on-Chip (NoCs). Interconnect performance often determines system throughput more than individual IP speed.
Architecture Evolution:
| Generation | Topology | Scalability | Examples |
|---|---|---|---|
| Shared bus | Single bus + arbiter | 2-5 masters | AMBA AHB |
| Crossbar | Full NxM switch | 8-16 ports | AXI crossbar |
| Ring | Circular point-to-point | 10-20 agents | Intel ring |
| Mesh NoC | 2D grid of routers | 100+ agents | ARM CMN |
| Hierarchical | Multi-level mixed | 1000+ agents | Modern SoC fabrics |
AMBA AXI Protocol: Dominant on-chip protocol with five independent channels (Write Address, Write Data, Write Response, Read Address, Read Data). Key features: burst transactions, out-of-order completion using transaction IDs, outstanding transactions, and QoS signaling.
NoC Design: For complex SoCs: Router architecture — input-buffered with virtual channels, 2-4 cycle per-hop latency; Topology — 2D mesh (regular, easy), torus (lower diameter), or custom; Routing — deterministic X-Y (simple, deadlock-free) vs. adaptive (better throughput); Flow control — credit-based or on/off with virtual channels preventing head-of-line blocking.
Coherent Interconnect: Multi-core cache coherence via: snoop-based (broadcast, scales to ~16 cores), directory-based (point-to-point, scales to 100+), or hybrid. Coherence protocols (MOESI, CHI) implemented in distributed home/slave nodes.
QoS and Arbitration: Priority-based (high-priority wins), bandwidth regulation (token buckets), deadline-aware scheduling (real-time bounds), and traffic isolation (preventing starvation via partitioning).
On-chip interconnect is the central nervous system of modern SoCs — its bandwidth, latency, and fairness create the performance envelope within which every IP operates.