Parasitic Extraction

Parasitic extraction: the wires themselves slow the chip downTurn the routed metal into R and C so timing sees the real, loaded delay of every net1 · Where they come froma wire is not an ideal connectiondrvrcvR (metal)C to groundCc coupling to the neighbor netEvery metal segment has seriesresistance, capacitance to ground, andcoupling capacitance to its neighbors.Longer, narrower, denser wires carrymore R and C — and more delay.2 · RC delay on the netR and C make the edge arrive lateideal steploaded (RC)delaydelay grows with R×C (≈ wire length²)The tool models each net as an RC treeand writes it to a SPEF file. Timing thenre-analyzes paths with real wire loads —post-route slack, not the optimisticpre-route estimate.3 · What extraction feedsthe numbers signoff runs onSPEF → timingstatic timing uses real RC to sign offsetup and hold at every corner.Crosstalk & noisecoupling caps let tools model a neighborswitching and glitching a quiet net.Power & IR / EMwire R sets IR-drop and electromigrationlimits on the power grid.Accuracy vs runtimeFull 3D field solve is most accurate butslow; rule-based extraction is fast andgood enough for most nets. Tools mixboth — solver only where it matters.ResistanceSeries R of the metal — longer andnarrower wires resist more.CapacitanceTo ground and to neighbors — setshow much charge each edge must move.SPEF → signoffThe extracted RC that makes timing,noise and power analysis real.

Parasitic Extraction — computing the resistance (R) and capacitance (C) of every wire and via in a chip layout, essential for accurate timing and power analysis.

Why Extraction?

  • Wires are not ideal — they have resistance (slows signals) and capacitance (stores charge)
  • At advanced nodes, interconnect RC delay dominates over transistor delay
  • Without extraction, timing analysis is meaningless

What Is Extracted

  • Wire resistance (proportional to length/width)
  • Wire-to-wire coupling capacitance (causes crosstalk)
  • Wire-to-ground capacitance
  • Via resistance (can be significant for long via stacks)

Extraction Types

  • RC (typical): Resistance and capacitance network
  • RCC (with coupling): Includes capacitive coupling between adjacent wires (for crosstalk analysis)
  • RLC: Includes inductance (for high-speed I/O and power grid analysis)

Flow

1. Extract parasitics from layout → SPEF file (Standard Parasitic Exchange Format)
2. Feed SPEF into STA tool for accurate timing
3. Feed into power analysis for accurate switching power

Tools: Synopsys StarRC, Cadence Quantus, Siemens xACT

Parasitic extraction is the bridge between physical design and signoff — it translates geometry into electrical reality.

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