Partial Via-First

Partial via-first is a hybrid dual-damascene integration sequence that starts etching the via before the trench is even patterned, but deliberately stops that via etch partway through — finishing it later, together with the trench, in a single combined etch step. It's a compromise between two older approaches, via-first and trench-first, each of which solved one problem while creating another, and partial via-first exists specifically to get the alignment benefit of starting early without inheriting the defect risk of finishing early too.

Partial Via-First: Four Steps 1. Via lithography pattern the via opening 2. Partial via etch only 50-70% depth 3. Trench lithography pattern over the shallow via 4. Combined etch trench + via finish together A shallow partial via is far easier to protect through step 3's lithography than a full-depth via would be — and its final depth gets set precisely by step 4's trench etch.

Via-first, the older approach that partial via-first was built to improve on, etches the via completely before the trench is patterned — and that early completion is exactly what causes problems during the trench step. With a fully-etched, full-depth via already open, patterning the trench on top of it means photoresist has to coat and expose over a deep, narrow opening — resist tends to pool unevenly or thin out at the via's edges, and the resulting lithography can suffer real defects precisely because the topography it's working over is already so dramatically uneven. Via-first's advantage was alignment simplicity (the via is defined before anything else complicates the geometry), but that advantage came paired with a genuine lithographic defect risk during the subsequent trench step.

Trench-first, the other older approach, flips the order entirely — etching the trench first and the via afterward — which solves the lithography problem but creates an alignment problem instead. With the trench etched first, the via lithography and etch happen on a comparatively flat, more lithography-friendly surface, avoiding via-first's resist and topography issues. But the via now has to be aligned precisely within an already-etched trench, and getting that final via depth and position right, after the trench is already fully formed, introduces its own control and uniformity challenges that via-first's earlier via-first-then-trench order didn't have.

Partial via-first splits the difference by starting the via early, for the alignment benefit, but stopping it well short of full depth before trench lithography begins. Etching the via only 50 to 70 percent of its target depth leaves far less topographic disruption for the trench lithography step to deal with than a fully-etched via-first via would, meaningfully reducing the resist and lithographic defects that plagued the original via-first approach. At the same time, the via still exists as a defined, aligned feature before trench patterning happens, preserving much of via-first's alignment-simplicity advantage that trench-first gave up.

The trench etch step does double duty, finishing the partial via at the same time it etches the trench to its own target depth — and that shared completion is where partial via-first gets its real control advantage. Rather than the via's final depth being set entirely during its own dedicated etch step, it ends up determined largely by the combined trench-and-via etch that happens afterward, which tends to produce more uniform via depth across the wafer than completing the via entirely in isolation would. This shift in which process step actually determines final via depth is the core engineering insight behind the whole technique — moving the final via depth to be an output of the trench etch, which is typically a more mature, well-controlled process step.

Partial via-first's main payoff shows up as fewer resist and etch defects during trench lithography, which translates directly into better yield at advanced nodes where aspect ratios have gotten punishingly tight. As interconnect dimensions have shrunk, the aspect ratio of a fully-etched via (its depth relative to its width) has grown correspondingly larger, making via-first's topography problem progressively worse with every generation of scaling. Partial via-first's reduced via depth at the point trench lithography happens directly lowers that aspect-ratio-driven defect risk, which is exactly why hybrid approaches like this one became standard practice as the industry kept pushing interconnect pitches tighter than the original, simpler via-first and trench-first approaches could comfortably support.

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