Peripheral BGA
Peripheral BGA is a ball-array layout that concentrates solder balls in the outer rows near a package's edges while leaving the center partially or fully empty — deliberately sacrificing some of a full array's total connection count to make the resulting PCB dramatically easier, and cheaper, to route. It's a cost-and-manufacturability compromise, aimed squarely at the moderate-pin-count devices where a full-array BGA's hardest routing problem simply isn't worth paying for.
Interior balls in a full-array BGA are structurally the most expensive connections a board has to route, which is exactly the problem peripheral BGA sidesteps by simply not having any. A ball sitting in the middle of a dense array has no direct path to the board's outer edge without threading through — or drilling a via straight through — whatever other balls and traces surround it, often requiring the signal to dive down through multiple internal board layers before it can escape to where it actually needs to go. An edge ball, by contrast, can often escape almost directly outward with a short trace on the board's top layer, no buried via or extra layer required. Peripheral BGA's whole value proposition is built on eliminating the first category of connection entirely.
Fewer total board layers is the direct, measurable payoff of avoiding interior-ball routing, and board layer count is one of the largest cost drivers in PCB fabrication. Every additional layer a board needs adds real manufacturing cost and complexity, and interior BGA connections are frequently the specific reason a board needs more layers than it otherwise would — without them demanding buried vias and extra routing layers, a board built around a peripheral BGA can often get away with meaningfully fewer layers than the equivalent full-array package would require. For moderate-pin-count products where cost sensitivity is real, this layer-count reduction can be the deciding factor in choosing peripheral BGA over a denser alternative.
Assembly process windows also tend to be broader for peripheral BGA layouts, which is a secondary but genuinely real manufacturing benefit beyond the board-cost savings alone. A simpler layout, with fewer tightly-packed interior connections to get right, generally gives reflow and placement processes more margin for minor variation before a defect actually results — not because peripheral BGA assembly is fundamentally different from full-array assembly, but because there's simply less densely-packed complexity for anything to go wrong with in the first place.
The real cost of this simplification is a lower total ball count for a given package size, which makes peripheral BGA a genuinely poor fit for any device that actually needs maximum I/O density. A design that requires every connection a full-size package footprint could theoretically support should not reach for peripheral BGA, since depopulating the center directly removes usable connections that a full array would have provided. This is precisely why peripheral BGA sits in a specific niche — devices with moderate, not maximal, I/O requirements — rather than functioning as a general-purpose replacement for full-array BGA across the board.
Ball-map planning for a peripheral BGA layout still requires real engineering judgment, specifically around which signals get the limited edge positions available. Even with a reduced total connection count, not every signal is equally important, and critical power connections and high-speed nets generally get priority placement in the most favorable edge positions, while less timing- or power-sensitive signals fill in the remaining available spots. Getting this allocation right — rather than simply filling edge positions in whatever order they happen to come up in a design tool — is what separates a peripheral BGA layout that actually delivers on its promised simplicity from one that still ends up fighting routing or signal-integrity problems despite the reduced ball count.