Place and Route Basics

Place & route: turn a gate-level netlist into a manufacturable layoutDecide where every cell sits, then wire them on the metal stack — all while meeting timing1 · Floorplan & placementmacros pinned, cells packed in rowsSRAMmacrostandard cells fill the rows between macrosPlacement chooses an (x,y) for everycell to shorten wires and hit timing,while leaving room to route andspreading heat and power draw evenly.2 · Routing the metal stacklayers alternate direction, vias connect— horizontal (Mx)| vertical (My)● viaGlobal routing assigns nets to regions;detailed routing lays exact tracks andvias, layer by layer, with no shorts orspacing violations. Congestion = failure.3 · What it optimizesthe PPA loop, run to signoffTimingclose setup & hold on every path; buffer,resize and legalize cells to fix slack.Congestion & areakeep routing demand under track supply;denser = smaller die, but harder to wire.Power & IRbuild the power grid, cap switching power,hold IR-drop within budget.Iterate to signoffPlace → route → analyze timing/DRC →engineering-change-order fixes → repeatuntil the layout is DRC-clean and everycorner meets timing. Then tape-out.PlacementWhere each cell sits — sets wirelength, timing and routability.RoutingWire the nets across metal layersand vias with zero DRC violations.Timing closureThe loop that makes every path meetits clock — the hard part of P&R.

Place and Route (PnR) — the automated process of positioning millions to billions of standard cells and connecting them with metal wires to create the physical chip layout.

Placement

1. Global Placement: Distribute cells across the floorplan to minimize estimated wire length
2. Legalization: Snap cells to legal row positions (standard cell rows)
3. Detailed Placement: Fine-tune positions to optimize timing and congestion

Clock Tree Synthesis (CTS)

  • Build balanced clock distribution network
  • Goal: Minimize clock skew (arrival time difference between registers) to < 50ps
  • Techniques: H-tree, mesh, or hybrid topologies with buffers and inverters

Routing

1. Global Routing: Plan approximate wire paths (which routing channels to use)
2. Detailed Routing: Determine exact wire geometry on metal layers, respecting design rules
3. DRC-clean routing: Fix any spacing, width, or via violations

Optimization Iterations

  • Fix setup violations: Upsize drivers, add buffers, reroute
  • Fix hold violations: Insert delay buffers
  • Fix congestion: Move cells, spread logic
  • Fix IR drop: Widen power stripes, add vias

Tools: Synopsys ICC2, Cadence Innovus, Synopsys Fusion Compiler

PnR transforms the abstract netlist into a physical layout ready for manufacturing — the culmination of the design flow.

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