PLL Design Clock Generation
PLL and DLL Clock Generation is the fundamental on-chip frequency synthesis and phase alignment technique that generates stable, low-jitter clock signals from a reference crystal oscillator — enabling all synchronous digital operations and high-speed I/O timing in modern SoCs.
PLL Architecture:
- Phase-Frequency Detector (PFD): compares reference clock phase and frequency to feedback clock — generates UP/DOWN pulses proportional to phase error with a dead zone typically < 100 ps to minimize jitter
- Charge Pump: converts PFD output pulses to analog current that charges/discharges the loop filter — current mismatch between UP and DOWN sources creates reference spurs at multiples of the reference frequency
- Loop Filter: passive or active RC network converts charge pump current to VCO control voltage — second-order filter (one zero, two poles) provides type-II loop behavior with programmable bandwidth (1-10 MHz)
- VCO (Voltage-Controlled Oscillator): ring oscillator (3-9 stages) or LC oscillator converts control voltage to output frequency — LC VCOs achieve ~10× better phase noise than ring VCOs but require on-chip inductors
Fractional-N PLL:
- Sigma-Delta Modulation: dynamically switches between integer divider ratios to achieve fractional-average division — quantization noise shaped to high frequencies where loop filter attenuates it
- Fine Frequency Resolution: fractional-N achieves sub-Hz frequency steps compared to reference-frequency steps in integer-N — essential for SerDes, wireless, and spread-spectrum applications
- Spurious Tones: sigma-delta modulator periodicity can create fractional spurs — randomized dithering and higher-order (3rd-4th order MASH) modulators push spurs below noise floor
DLL Architecture:
- Delay Line: voltage-controlled delay chain adjusts total delay to equal one reference clock period — feedback loop locks when the delayed clock edge aligns with the next reference edge
- Advantages Over PLL: unconditionally stable (first-order loop), no frequency multiplication (no jitter accumulation), faster lock time — but cannot generate frequencies different from reference
- Applications: DRAM clock alignment (DDR I/O timing), multi-phase clock generation for interleaved ADCs, and duty-cycle correction
Jitter and Phase Noise:
- Random Jitter (RJ): thermal and flicker noise in VCO and charge pump — Gaussian distribution with standard deviation typically 0.5-5 ps RMS
- Deterministic Jitter (DJ): reference spurs, supply-induced jitter, and substrate coupling — bounded in amplitude, appears as concentrated energy at specific frequencies
- Phase Noise Specification: characterized as dBc/Hz at specific offset frequencies — -100 dBc/Hz at 1 MHz offset is typical for ring-oscillator PLLs; LC PLLs achieve -115 to -130 dBc/Hz
- Jitter Transfer: PLL acts as low-pass filter for reference jitter and high-pass filter for VCO jitter — bandwidth selection balances tracking of reference vs. filtering of VCO noise
PLL and DLL circuits are among the most ubiquitous analog/mixed-signal IP blocks in modern semiconductor design — a typical SoC contains 5-20 PLL instances generating clocks for CPU cores, memory interfaces, SerDes lanes, and peripheral buses.