Poly Fill

Poly fill consists of dummy polysilicon shapes inserted into empty regions of the polysilicon layer to achieve uniform pattern density — ensuring consistent CMP planarization and etch behavior during gate patterning, which is one of the most critical steps in semiconductor fabrication.

Why Poly Fill Is Important

• The polysilicon (or metal gate) layer defines transistor gates — the most dimension-critical features on the chip.
• CMP Dependency: At advanced nodes, gate patterning or replacement metal gate (RMG) processes involve CMP steps whose uniformity depends on local pattern density.
• Etch Loading: Poly etch rate varies with local pattern density — uniform density produces more consistent CD (critical dimension) control.
• Stress Uniformity: Non-uniform poly density creates differential stress that can affect transistor threshold voltage.

Poly Fill Characteristics

• Shape: Small rectangular dummy poly shapes, sized according to design rules.
• Isolation: Must be placed on field oxide (STI) — never over active regions, as that would create unintended transistors.
• Spacing: Minimum spacing maintained from functional poly gates to prevent parasitic effects and ensure the fill doesn't interfere with device operation.
• Connectivity: Typically floating (unconnected) or tied to ground through contacts.

Poly Fill Constraints

• No Overlap with Active: The most critical constraint — dummy poly on active regions would create parasitic transistors that alter circuit behavior.
• Exclusion Zones: Keep fill away from device regions, sensitive analog circuits, and specific IP blocks that specify no-fill zones.
• Gate Length Rules: Even dummy poly must satisfy minimum width and spacing rules for the poly layer.
• Density Targets: Must achieve the foundry's specified density range (varies by process, typically 15–60%).

Poly Fill at Advanced Nodes

• At FinFET nodes (14 nm and below), the poly layer is used for the gate patterning step during gate-last (RMG) processing.
• Continuous Poly (CPODE): Some advanced nodes use continuous poly lines across the die with designated "cut" locations — fill is inherent in the continuous line pattern.
• Cut Poly: The "gate cut" layer removes poly segments where they are not needed — the remaining continuous poly provides inherent density uniformity.

Poly fill is essential for gate CD uniformity — inconsistent poly density directly translates to transistor threshold voltage variation and performance degradation across the die.