Post-Exposure Bake (Peb)
# Post-Exposure Bake (PEB)
Post-exposure bake (PEB) is the controlled thermal step between exposure and development that converts a latent chemical image into a developable resist image. In a chemically amplified resist, exposure creates acid; PEB supplies the time and temperature for that acid to catalyze deprotection or cross-linking. The useful image is therefore made jointly by optical or electron exposure, reaction kinetics, molecular transport, and the developer—not by exposure alone.
PEB is not a second soft bake. Soft bake primarily removes casting solvent and stabilizes the coated film before exposure. PEB deliberately advances the exposed chemistry afterward. Its process window must preserve dose sensitivity and chemical contrast while limiting lateral blur, stochastic variability, profile distortion, and wafer-scale CD signatures.
## What PEB controls
In a positive-tone chemically amplified resist, photoacid catalyzes removal of protecting groups from the polymer. The converted regions become soluble in developer. In a negative-tone system, thermal chemistry may instead promote cross-linking or another reaction that makes exposed material less soluble. Metal-oxide and molecular resists can involve condensation, ligand loss, redox, or other material-specific pathways. The chemistry must therefore be named before interpreting a temperature or time trend.
For a simple diffusion picture, a characteristic transport length scales as
and a reaction rate or diffusivity often has an Arrhenius-like temperature dependence. This explains why temperature errors are not equivalent to proportional time errors and why matching only the nominal setpoint is inadequate. Real resists depart from the simple model: acid can be trapped or neutralized, diffusivity can change as deprotection proceeds, polymer free volume and residual solvent matter, volatile products can leave the film, and interfaces can alter reaction and transport.
The desired thermal history produces sufficient conversion and contrast without allowing the chemical image to spread beyond its edge-placement budget. Too little effective bake can cause incomplete deprotection, low sensitivity, scum, poor contrast, or weak process latitude. Too much can shift CD, round corners, bridge spaces, reduce image-log-slope benefit, alter sidewall shape, or increase pattern-to-pattern bias. The direction of CD change depends on tone, feature type, resist model, developer, and the definition of the measured edge; it should not be generalized from one line-space experiment.
## The wafer experiences a trajectory, not a setpoint
The relevant input is the wafer’s temperature-versus-time history. It includes approach to the plate, contact or proximity gap, ramp, dwell, lift, transfer, and cooling. Wafer thickness and bow, backside particles, plate flatness, thermal contact, zone calibration, exhaust, local airflow, incoming wafer temperature, and film stack can all change that history. A display reading is a controller variable, not proof of wafer temperature.
Exposure-to-PEB delay is also part of the process. During the delay, acid, quencher, absorbed water, and airborne molecular contaminants can change the near-surface chemistry. Base contamination may neutralize acid and create a less-reacted surface layer or time-dependent CD shift. Track scheduling must therefore control the delay distribution and exceptional queue events, not merely its average.
Cooling after PEB matters because reaction and transport do not stop at the instant the plate command ends. A repeatable chill-plate sequence defines where the thermal reaction is arrested before development. Mixing wafers with different queue, bake, and cool trajectories under one nominal recipe creates hidden populations in the metrology data.
## Failure signatures and diagnosis
PEB excursions rarely announce themselves as a single universal defect. They appear through coupled signatures:
| Observation | Plausible PEB-related mechanism | Discriminating evidence |
|---|---|---|
| Radial CD shift | plate temperature/gap, wafer bow, cooling geometry | wafer-coordinate map, reference thermometry, plate-zone history |
| Repeatable module fingerprint | heater-zone calibration, plate flatness, exhaust or chill module | matched wafers across modules and time |
| Surface inhibition or T-top | airborne base, delay sensitivity, interface chemistry | controlled delay/ambient split and cross-section |
| Rounded corners or space loss | excessive effective diffusion/reaction | temperature-time matrix, pitch/orientation split |
| Scum or incomplete clearing | insufficient conversion, weak exposure, developer interaction | dose × PEB × develop factorial experiment |
| Local stochastic failures | photon/material statistics, quencher and acid distribution | repeated dense sampling, defect review, resist-lot comparison |
| ADI-to-AEI mismatch | resist profile changes transfer nonlinearly in etch | paired after-develop and after-etch metrology |
Diagnosis must separate correlation from mechanism. A radial after-develop CD map does not prove that PEB caused it: resist thickness, scanner focus/dose, develop hydrodynamics, metrology bias, and incoming-film topography can make similar maps. Module swaps, controlled splits, reference wafers, and paired measurements before and after etch are more informative than a large unstructured history table.
## Metrology and sampling
PEB qualification should include CD across feature types and pitches, profile or sidewall information, line-edge/line-width roughness with a declared bandwidth, residual film or scum, defectivity, and downstream pattern transfer. Top-down CD alone can miss footing, T-top, undercut, resist loss, and three-dimensional profile changes. CD-SEM, optical critical-dimension metrology, AFM, and cross-sectional SEM/TEM observe different measurands and averaging volumes; agreement is not automatic.
A useful experiment crosses exposure dose and focus with PEB temperature and time, then repeats critical points across hotplates, resist lots, wafer positions, and delay conditions. Randomization prevents time drift from masquerading as a recipe effect. Replication estimates repeatability and interactions. Sampling should preserve wafer, field, layout, orientation, module, and time coordinates rather than pooling them into one standard deviation.
Gauge capability matters because apparent recipe sensitivity can be an edge-detection, charging, shrinkage, sampling, or model effect. Measurement recipes must be versioned alongside process recipes. Any model used to infer acid diffusion or conversion from final CD is conditional on its resist, feature, exposure, development, and measurement assumptions; the inverse problem may not have a unique answer.
## Control strategy
A production control plan records the complete wafer genealogy: resist and substrate lot, coat/soft-bake state, exposure conditions, exposure-to-PEB delay, PEB module and zone state, commanded and measured timing, cooling path, developer module, metrology recipe, and downstream etch chamber. Control charts should distinguish within-wafer signatures, module matching, wafer-to-wafer drift, and special events.
Run-to-run correction is appropriate only for a stable, identified relationship with adequate measurement latency and explicit actuator limits. Feed-forward from measured film thickness or incoming wafer temperature may be useful after qualification. Feedback from after-develop CD may adjust a bounded PEB or exposure actuator for later wafers, but cross-compensation can hide equipment faults and can improve one monitor while degrading profile, roughness, defectivity, or etch transfer.
Interlocks should stop or hold material for heater-zone faults, out-of-family ramp/dwell traces, excessive exposure-to-bake delay, failed cooling, backside contamination, ambient excursions, or stale metrology. A safe controller stores the baseline recipe, correction magnitude, reason code, model/version, validity range, and rollback condition. Maintenance—not APC—is the correct response to a damaged plate, drifting sensor, or contaminated module.
## Qualification checklist
- Define resist chemistry, tone, film stack, feature population, developer, and downstream transfer target.
- Calibrate wafer thermal history rather than relying only on the plate sensor and displayed setpoint.
- Bound exposure-to-bake and bake-to-develop delays, including queue and recovery scenarios.
- Map hotplate and chill modules with coordinate-preserving CD/profile metrology.
- Use factorial splits to separate exposure, PEB, and development interactions.
- Verify the selected window at ADI and after etch, including roughness and defectivity.
- Perform gauge studies and keep process and metrology recipe versions traceable.
- Qualify module matching, resist-lot changes, maintenance recovery, and long-run conditioning.
- Put bounded APC behind fault detection, interlocks, audit logs, and a proven rollback path.
The central engineering idea is simple: PEB is controlled reaction and transport, not generic heating. Exposure determines where reactive species are generated; the bake determines how far and how completely their chemistry proceeds; development reveals the resulting solubility field; etch decides whether that resist image was actually useful. Art-level PEB control follows that entire causal chain.