Process Node
Semiconductor Process Nodes are the generational labels used to describe successive advances in chip manufacturing technology, originally representing a physical feature size (gate length or metal pitch) but now serving as marketing terminology that captures a bundle of improvements in transistor density, power efficiency, and performance — making the "nm" number a trademarked capability designation rather than a literal physical measurement.
Why "nm" No Longer Means Nanometers
In the 1990s and early 2000s, the process node name corresponded directly to the transistor gate length:
- 250nm (1997): Gate length = 250nm
- 130nm (2001): Gate length = 130nm
- 90nm (2004): Gate length = 90nm
This correspondence ended around 2003-2007. Today:
- TSMC N3 (3nm): Minimum metal pitch ~20nm; smallest feature ~12nm — nothing is actually 3nm
- Intel 7 (previously called 10nm): Renamed to match competitor marketing language
- TSMC N2 (2nm): Gate-all-around nanosheets, smallest features ~10nm
The node name is now a relative performance/density label. TSMC N3 is denser and more power-efficient than N5 — but the "3" is a generational marker, not a dimension.
Node Roadmap and Transistor Architecture Evolution
| Node Era | Representative Nodes | Architecture | Key Change |
|---|---|---|---|
| Planar | 250nm → 28nm | Planar MOSFET | Simple flat channel; hit leakage limits at 28nm |
| FinFET | 22nm → 3nm | 3D Fin transistor | Fin wraps gate on three sides; better electrostatic control |
| GAA Nanosheet | 2nm → 1nm | Gate-all-around | Sheet of silicon fully surrounded by gate; maximum control |
| CFET | <1nm (future) | Complementary FET | NMOS and PMOS stacked vertically; ultimate density |
Key Nodes and Their Significance
28nm — The Last Planar Node
- Cost: ~$3,000/wafer (very mature)
- Used for: MCUs, IoT chips, display drivers, analog, automotive
- Why it persists: Cost-optimized, abundant foundry capacity, no EUV needed
- Still in production at TSMC, Samsung, GlobalFoundries, UMC, SMIC
7nm — First Mass EUV Production
- TSMC 7nm (2018): First node to use EUV lithography in production at scale
- AMD Zen 2 (2019), Apple A13 Bionic — transformed PC and mobile performance
- 160M transistors/mm² for TSMC N7
- Wafer cost: ~$9,000
5nm — Mobile AI Mainstream
- TSMC N5 (2020), Samsung 5LPE
- Apple M1 (2020): First laptop processor to demolish x86 performance-per-watt
- 171M transistors/mm² for TSMC N5
- Wafer cost: ~$13,000
3nm — FinFET Limit
- TSMC N3 (2022), N3E (2023): Still FinFET architecture
- Samsung 3GAE: First commercial GAA node (2022), lower yield than TSMC initially
- 291M transistors/mm² for TSMC N3E
- Apple A17 Pro, M3 series manufactured on TSMC N3
- Wafer cost: ~$18,000-$20,000
2nm — GAA Transition
- TSMC N2 (2025): Industry's debut of Gate-All-Around (GAA) in volume production
- Samsung SF2 (2025): Samsung's 2nm GAA
- Intel 20A/18A (2025): Intel's GAA (RibbonFET) with PowerVia backside power delivery
- ~400M+ transistors/mm² target
- Wafer cost: $20,000-$25,000+
Why Process Nodes Matter for AI Chips
AI chips are the most voracious consumers of leading-edge process nodes:
| Chip | Node | Die Size | Transistors | Application |
|---|---|---|---|---|
| NVIDIA H100 SXM | TSMC N4 (4nm) | 814 mm² | 80 billion | AI training |
| NVIDIA B200 | TSMC N3P | 1,034 mm² | 208 billion | AI training |
| Apple M4 | TSMC N3E | 308 mm² | 28 billion | AI PC/mobile |
| AMD MI300X | TSMC N5/N6 | Multi-tile | 153 billion | AI training |
| Google TPU v5p | TSMC N4 | Confidential | — | AI training |
Each new node delivers approximately:
- 15-20% performance improvement at same power
- 30-40% power reduction at same performance
- ~1.6x density increase (more transistors per mm²)
Economics: The Leading-Edge Cost Spiral
| Node | Wafer Cost | EDA Cost | Mask Set Cost | Design Cost (SoC) |
|---|---|---|---|---|
| 28nm | ~$3,000 | Low | ~$1.5M | ~$30M | ||
| 16nm FinFET | ~$5,000 | Medium | ~$5M | ~$100M | ||
| 7nm | ~$9,000 | High | ~$15M | ~$300M | ||
| 5nm | ~$13,000 | Very High | ~$25M | ~$500M | ||
| 3nm | ~$18,000 | Extreme | ~$40M | ~$800M | ||
| 2nm | ~$22,000+ | Extreme | ~$60M+ | ~$1B+ |
This cost explosion is driving the chiplet revolution: only the most performance-sensitive circuits (CPU cores, GPU cores) use leading-edge nodes, while I/O, analog, and memory use older, cheaper nodes. NVIDIA's GB200 uses TSMC N3 for the compute die and N5 for the NVLink die.
CHIPS Act and Geopolitics
Semiconductor manufacturing geography has become a national security issue:
- TSMC: 60% of global advanced logic capacity (Taiwan) — building factories in Arizona (N4), Japan (N12/N6), Germany (N22/N28)
- Samsung: Second largest advanced foundry (South Korea) — Taylor, Texas fab under construction
- Intel Foundry: Intel 18A targets European and US market; $8.5B CHIPS Act funding
- SMIC (China): Limited to ~7nm (N+1/N+2) due to US export controls on EUV scanners
- Export Controls: BIS (Bureau of Industry and Security) restricts EUV export to China, blocking <7nm access
Process node leadership determines AI chip leadership — and AI chip leadership increasingly determines economic and military competitiveness.