RC Delay

RC delay is the time a signal takes to propagate through a chip's wiring, caused by the unavoidable combination of a wire's electrical resistance (R) and the capacitance (C) it forms with neighboring wires and layers. Below roughly 90 nanometers, this delay stopped being a minor side effect and became the dominant limit on how fast signals can move across a chip — overtaking transistor switching speed itself as the thing that actually determines performance.

RC delay exists because every wire on a chip is, electrically, a tiny resistor in series with a tiny capacitor, and switching a signal means charging that capacitor through that resistor. A wire has resistance because real metal isn't a perfect conductor, and it has capacitance because it sits close to neighboring wires, the layers above and below it, and the substrate — each of those gaps acts like a capacitor plate pair. Driving a signal down that wire means pushing charge through the resistance to fill the capacitance, and that process takes a nonzero amount of time that scales directly with how large R and C both are.

The balance between gate delay and wire delay flipped as process nodes shrank, which is the real reason RC delay became such a major design concern. At older nodes (roughly 180 nanometers and above), transistor switching speed was the dominant delay in most paths, and wires were treated as nearly ideal connections. Below about 90 nanometers, wires got both thinner and more closely packed as part of normal scaling, and interconnect delay overtook transistor delay as the larger contributor on many chip-critical paths. This flip changed what "making a chip faster" actually meant in practice — optimizing transistors alone stopped being enough once the wires connecting them became the real bottleneck.

Scaling makes RC delay worse in both directions simultaneously, which is what makes it such a stubborn problem rather than a one-time fix. Shrinking a wire's cross-section to fit a smaller process node directly raises its resistance, because a thinner, narrower conductor resists current flow more. At the same time, packing wires closer together to fit more routing in less area directly raises capacitance, because capacitance grows as conductors get closer together. Every generation of process scaling has pushed both of these numbers in the wrong direction at once, which is exactly why interconnect engineering has needed continuous, dedicated material and architectural innovation rather than simply riding transistor scaling along for free.

Lowering resistance drove one of the most consequential materials transitions in chip manufacturing history: the industry-wide switch from aluminum to copper wiring in the late 1990s. Copper's resistivity is meaningfully lower than aluminum's, directly cutting R for the same wire geometry — a genuine win that required an entirely new fabrication approach (damascene processing) because copper can't be dry-etched the way aluminum could. At the most advanced nodes, copper itself starts running into trouble: at very narrow wire widths, electron scattering off the wire's own surfaces and grain boundaries raises effective resistivity faster than copper's bulk advantage can compensate for, which is why materials like ruthenium and molybdenum are now being explored specifically for the narrowest interconnect levels, where their different scattering behavior gives them an edge copper no longer has.

Lowering capacitance pushed the industry toward low-k dielectrics, and eventually toward structures that barely qualify as "dielectric" at all. Standard silicon dioxide, with a dielectric constant around 3.9, was replaced at advanced nodes by low-k materials (roughly 2.5 to 3.0) and later ultra-low-k materials (down to about 2.0 to 2.5), often made porous specifically to lower their effective dielectric constant further. Some advanced interconnect stacks go a step further and introduce deliberate air gaps between the most sensitive, tightly spaced wires — since air's dielectric constant is close to 1.0, replacing solid dielectric with air directly minimizes capacitance exactly where it matters most. Beyond materials, circuit and layout techniques matter just as much: inserting repeater buffers breaks a single long, slow RC path into several shorter, faster ones, and simply routing wires shorter — through better place-and-route algorithms and more available metal layers to spread connections across — reduces both R and C by reducing the wire length itself, often the single most effective lever available.