Reflections
Reflections in signal integrity are signal energy that bounces back from impedance discontinuities along a transmission path — creating ringing, overshoot, undershoot, and signal distortion that degrade signal quality and can cause data errors.
Why Reflections Occur
- A signal propagating along a transmission line encounters an impedance mismatch when the characteristic impedance ($Z_0$) of the line changes — at connectors, vias, width changes, branches, or the termination.
- At the mismatch point, part of the signal energy continues forward (transmitted) and part bounces back (reflected).
- The reflection coefficient ($\Gamma$) determines how much is reflected:
$$\Gamma = \frac{Z_L - Z_0}{Z_L + Z_0}$$
Where $Z_L$ is the impedance at the discontinuity and $Z_0$ is the line impedance.
Reflection Scenarios
| Termination | $Z_L$ | $\Gamma$ | Effect |
|---|---|---|---|
| Open Circuit | ∞ | +1 | Full positive reflection — voltage doubles |
| Short Circuit | 0 | −1 | Full negative reflection — voltage cancels |
| Matched | $Z_0$ | 0 | No reflection — all energy absorbed |
| Partial Mismatch | ≠ $Z_0$ | Between −1 and +1 | Partial reflection |
How Reflections Manifest
- Ringing: Multiple reflections bouncing between mismatched source and load create oscillating voltage at the receiver — the signal "rings" around the final value.
- Overshoot: The signal exceeds VDD due to constructive reflection — may damage sensitive circuits or cause false logic states.
- Undershoot: The signal goes below ground — same concerns as overshoot.
- Staircase Waveform: The signal reaches its final value in steps as reflections arrive at successively reduced amplitudes.
- Settling Time: The signal takes multiple round-trip delays to settle — increased effective propagation delay.
Common Sources of Reflections
- Unterminated Lines: Lines without proper termination resistors — the most common source.
- Vias: Layer transitions change the impedance — especially via stubs (the unused portion of a through-hole via).
- Connectors: PCB connectors often have different impedance than traces.
- Trace Width Changes: Different widths have different $Z_0$.
- Branches/Stubs: T-junctions and stubs create impedance discontinuities.
- Package Transitions: Bond wires, bumps, and package traces may not match die or PCB impedance.
Termination Techniques
- Series Termination: Resistor at the driver output — driver impedance + resistor = $Z_0$. Simple, low power, but reflected wave must make round trip before settling.
- Parallel Termination: Resistor at the receiver end — matches $Z_L = Z_0$. Fast settling (no reflections from load) but draws DC current.
- Thevenin Termination: Resistor divider to VDD and VSS at the receiver — biases the line to mid-voltage.
- AC Termination: Series RC at receiver — provides AC impedance matching without DC current.
- On-Die Termination (ODT): Integrated termination resistors on the chip — used in DDR memory interfaces.
Reflections are the most fundamental signal integrity issue — understanding and controlling impedance matching is the first step in any high-speed design.