Retiming Optimization
Register Retiming is the logic optimization technique that moves flip-flops (registers) across combinational logic gates to balance path delays and minimize the clock period — without changing the functional behavior of the circuit, achieving higher operating frequency or reduced register count by repositioning the synchronization boundaries within the pipeline stages.
Why Retiming?
- After initial RTL design, pipeline stages often have uneven delays.
- Stage A: 2 ns logic delay. Stage B: 5 ns logic delay → clock period = 5 ns (bottleneck).
- Retiming: Move some logic from Stage B before the register → Stage A: 3.5 ns, Stage B: 3.5 ns → clock period = 3.5 ns.
- 30% frequency improvement without adding any logic or changing functionality.
Retiming Operations
| Operation | Description | Effect |
|---|---|---|
| Forward Retiming | Move register from input to output of gate | Balances delays forward |
| Backward Retiming | Move register from output to input of gate | Balances delays backward |
- Rules: A register can move through a gate if ALL inputs (or ALL outputs) have registers.
- When moving through a gate with N inputs: 1 register becomes N registers (fan-in expansion).
- When moving through a gate with N outputs: N registers become 1 register (fan-out compression).
Retiming Algorithms
- Leiserson-Saxe Algorithm: Models circuit as a graph with edge weights (delays) and register counts → solves a shortest-path / linear programming problem → finds optimal register placement for minimum clock period.
- Minimum Period Retiming: Minimize clock period with fixed number of registers.
- Minimum Register Retiming: Minimize register count while meeting target clock period.
Practical Considerations
- Reset values: Retimed registers may need different reset values → tool must handle initialization.
- Verification: Retiming changes register positions → formal equivalence checking required.
- Timing constraints: Cannot retime across clock domain boundaries or I/O interfaces.
- Memory elements: Cannot retime through RAMs/ROMs — only pure combinational logic.
Tool Support
- Design Compiler (Synopsys): `optimize_registers` command enables retiming during synthesis.
- Genus (Cadence): Built-in retiming optimization.
- Quartus/Vivado (FPGA): Retiming for FPGA pipeline optimization.
Register retiming is one of the most powerful automated optimization techniques in digital design — it extracts better performance from existing logic by intelligently repositioning registers, often achieving 10-30% frequency improvement at zero area cost, making it a standard step in high-performance synthesis flows.