Reverse Body Bias (Rbb)

Reverse Body Bias (RBB) is the technique of applying a voltage that increases the transistor threshold voltage ($V_{th}$) — making transistors harder to turn on, which dramatically reduces leakage current at the cost of slower switching speed, used primarily to cut standby power.

How RBB Works

• NMOS: The p-well (body) voltage is lowered below ground. For example, $V_{body} = -300$ mV.
• This increases $V_{th}$ by the body effect → higher barrier to channel formation → less subthreshold leakage.
• PMOS: The n-well voltage is raised above VDD. For example, $V_{body} = V_{DD} + 300$ mV.
• This increases $|V_{th}|$ for PMOS → less PMOS leakage.

RBB Effects

• Leakage Reduction: RBB of −300 to −500 mV typically reduces leakage by 3–10× — massive savings during standby.
• Speed Reduction: Higher $V_{th}$ means slower transistors — typically 10–25% speed degradation.
• The Trade-off: RBB is applied when the block is idle or in low-performance mode — the speed penalty doesn't matter.

When RBB Is Used

• Standby/Sleep Mode: When a block must remain powered (for state retention or fast wake-up) but isn't computing — RBB reduces leakage without full power gating.
• Fast Silicon Leakage Control: Chips on the fast end of the process distribution have excessive leakage. RBB brings their leakage back to acceptable levels.
• Thermal Management: As temperature increases, leakage rises exponentially. RBB can counteract thermally-induced leakage increase.
• Low-Performance Mode: During light workloads, apply RBB + lower frequency — maximum power efficiency.

RBB vs. Power Gating

• Power Gating: Disconnects the supply entirely → leakage drops to near zero. But the block loses state (needs retention) and has longer wake-up latency.
• RBB: Keeps the block powered and retains state automatically. Leakage reduced but not eliminated. Faster wake-up (just remove the bias).
• Use RBB when fast wake-up or state preservation without retention cells is needed.
• Use Power Gating when the idle period is long enough to justify the deeper sleep.

RBB Implementation

• Bias Generators: On-chip charge pumps generate the negative (for NMOS) or above-VDD (for PMOS) bias voltages.
• Well Contacts: Adequate well contacts throughout the design distribute the bias voltage uniformly.
• Triple-Well Structure: Required for independent NMOS body biasing in a p-substrate process — deep n-well isolates the p-well from the substrate.

RBB Limits

• Diminishing Returns: Beyond −500 mV, additional RBB provides progressively less leakage reduction.
• Junction Breakdown: Excessive reverse bias can approach junction breakdown voltage — must stay within safe limits.
• DIBL Sensitivity: At deep RBB, drain-induced barrier lowering (DIBL) effects can limit effectiveness.

Reverse body bias is the go-to technique for leakage reduction without power gating — it provides a fast, reversible way to reduce standby power while maintaining the block in a ready-to-operate state.