Schottky Barrier
A Schottky barrier is the potential energy barrier that forms at the interface between a metal and a semiconductor, and in the simplest ideal picture its height is set by the difference between the metal's work function and the semiconductor's electron affinity. Real metal-semiconductor interfaces routinely defy that simple formula, though, because surface states at the interface tend to pin the actual barrier height near the semiconductor's mid-gap energy regardless of which specific metal is used — a phenomenon called Fermi level pinning that has shaped decades of contact engineering specifically around working with, or around, this pinning effect.
Fermi level pinning on silicon specifically undermines the simple ideal barrier-height formula, because surface states at the metal-silicon interface create a dense population of localized electronic states that effectively lock the barrier height near the semiconductor's mid-gap energy regardless of which metal's work function is actually used. This pinning effect is exactly why metal selection for silicon contacts can't simply chase the lowest-work-function metal available and expect a correspondingly low barrier — the pinning behavior substantially decouples the achieved barrier height from the naive metal-work-function prediction, forcing contact engineering to work within, or specifically around, the pinning effect rather than against a simple, freely tunable formula.
Three distinct current-transport mechanisms operate across a Schottky barrier — thermionic emission over the barrier's energy peak, thermally-assisted tunneling through a partially reduced effective barrier, and direct tunneling through the barrier at very high doping — and which mechanism actually dominates a given contact's behavior depends specifically on barrier height, temperature, and doping concentration. This mechanism dependence matters practically because each transport mode produces a genuinely different current-voltage relationship, meaning accurately predicting or engineering a specific contact's electrical behavior requires knowing which mechanism actually dominates for that contact's specific conditions, not simply assuming the conventional thermionic-emission picture applies universally.
Low Schottky barrier height translates directly into lower contact resistance, which is exactly why titanium and titanium nitride are specifically favored for NMOS contacts — these metals happen to produce comparatively lower effective barrier heights on silicon relative to many alternative contact metals, even accounting for Fermi level pinning's general tendency to compress barrier-height variation across different metal choices. This metal-selection logic is a direct, practical consequence of the barrier-height-to-resistance relationship: even modest differences in effective barrier height among metals that all experience pinning still translate into measurably different contact resistance, which is exactly why metal choice remains a meaningful engineering lever despite pinning's compressing effect.
Schottky diodes exploit the absence of minority-carrier storage that distinguishes a metal-semiconductor junction from a conventional p-n junction, giving Schottky diodes genuinely fast switching and recovery behavior that makes them the preferred choice for high-speed rectification applications where a p-n diode's minority-carrier storage time would otherwise limit switching speed. This minority-carrier-storage absence isn't an incidental Schottky-diode property — it's the direct physical consequence of majority-carrier-dominated transport across a metal-semiconductor interface, fundamentally different from the minority-carrier injection a p-n junction depends on, which is exactly why Schottky diodes occupy a genuinely distinct performance niche from conventional diodes rather than simply being a minor variant.
Achieving a Schottky barrier height below roughly 0.1 eV has become a specific, explicit target for source/drain contact engineering at sub-5nm nodes, because contact resistance increasingly dominates total transistor resistance as every other transistor dimension continues shrinking, making barrier height reduction one of the highest-leverage remaining levers for continued performance scaling at these advanced nodes. This sub-0.1eV target illustrates exactly how consequential Fermi level pinning's constraint on achievable barrier height has become at advanced nodes — overcoming or working around pinning to reach genuinely ultra-low barrier heights is no longer an academic curiosity but a concrete, quantified engineering target directly tied to competitive transistor performance.