Self Aligned via

Self-Aligned Via (SAV) is the advanced CMOS interconnect process technique that uses etch selectivity between different dielectric materials to automatically position vias directly on top of metal lines without relying solely on lithographic overlay accuracy — eliminating via-to-metal misalignment that causes reliability failures and resistance increases, essential at sub-7nm nodes where the via diameter approaches the lithographic overlay tolerance and conventional via formation has unacceptable yield loss.

Why Self-Aligned Vias

Conventional via: Via hole patterned independently of underlying metal → relies on overlay.
Overlay accuracy: ±2-3nm at advanced nodes.
Metal line width: 14-20nm at sub-7nm nodes.
Via diameter: 12-18nm.
Problem: 3nm overlay error on 16nm metal line → via partially lands on dielectric → open or high resistance.
SAV: Via automatically centered on metal regardless of overlay error → robust process.

SAV Process Flow

Step 1: Form metal lines with selective cap
  [SiN cap]     [SiN cap]     [SiN cap]
  [Cu line]     [Cu line]     [Cu line]
  [Low-k ILD around lines]

Step 2: Deposit via-level ILD (SiO₂ or low-k)

Step 3: Etch via hole with selectivity to SiN cap
  - Via etch stops on SiN cap (selective)
  - Even if misaligned → etch goes through ILD but stops on SiN

Step 4: Break through SiN cap only where via lands on metal
  - Short directional etch removes SiN → exposes Cu below
  - Via centered on metal line by SiN cap geometry

Material Requirements

Layer	Material	Purpose
Metal cap	SiN or SiCN	Etch stop, defines via landing
Via ILD	SiO₂ or SiOC	Via dielectric
Metal line ILD	SiOCH low-k	Line dielectric
Etch selectivity	Via ILD : Metal cap > 10:1	Enables self-alignment

Key Etch Selectivity

Via etch (SiO₂ removal): C₄F₈/Ar plasma → etches SiO₂ rapidly.
Metal cap (SiN): Same plasma etches SiN slowly → 10-20:1 selectivity.
Result: Via etch naturally stops when it reaches the SiN-capped metal line.
Misalignment tolerance: Via can be misaligned by up to half the metal pitch → SiN cap still protects.

SAV in Dual Damascene

Fully self-aligned dual damascene: Both via and trench are self-aligned to lower metal.
Process: Selective etch stop layers at every metal interface.
Benefit: No metal-to-via or via-to-metal shorts from overlay → 5-10× yield improvement at tight pitch.

Challenges

Challenge	Issue	Mitigation
Extra caps increase RC	SiN has higher k than SiOC	Use thinnest possible cap (2-3nm)
Etch selectivity variations	Process drift reduces selectivity margin	Tight SPC on etch chemistry
Cap integrity	Thin cap must survive CMP	Optimize CMP pressure/slurry
Multi-cap integration	Different caps for via vs. line level	Complex integration scheme

Self-aligned via technology is the solution to the lithographic overlay crisis at advanced interconnect nodes — by encoding alignment information into the dielectric stack through selective etch stops rather than depending purely on overlay accuracy, SAV processes convert what would be catastrophic misalignment-driven yield loss into a robust, self-correcting patterning flow that is essential for achieving viable yields at sub-5nm technology nodes.

Self Aligned via

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