Semiconductor Cost
Semiconductor Cost Economics is the analysis of fabrication, packaging, and testing costs that determine the price per transistor and price per die — where a single leading-edge fab costs 20-30 billion to build and a 300mm wafer costs 10,000-20,000+ to process through 1000+ steps at advanced nodes.
Fab Construction Cost
| Node | Fab Cost | Example |
|---|---|---|
| 28 nm | 3-5B | TSMC Fab 15 |
| 7 nm | 10-12B | TSMC Fab 18 |
| 5 nm | 12-15B | Samsung S2 |
| 3 nm | 15-20B | TSMC Fab 18b |
| 2 nm | 20-28B | TSMC Arizona (projected) |
| Intel 18A | 25-30B | Intel Ohio (projected) |
Wafer Processing Cost
- Mature nodes (28nm): 2,000-3,000 per wafer.
- 7nm: 8,000-10,000 per wafer.
- 3nm: 15,000-20,000 per wafer.
- Cost breakdown: Lithography (30-40%), deposition (15-20%), etch (10-15%), implant (5%), metrology (5%), other (10-15%).
EUV Lithography Cost Impact
- ASML EUV scanner: 150-200M per tool.
- EUV throughput: 150-200 wafers/hour (vs. 300+ for DUV).
- 3nm requires 20+ EUV layers — EUV lithography dominates wafer cost.
- High-NA EUV (0.55 NA): 350-400M per tool — pushes wafer costs higher at 2nm.
Die Cost Calculation
$Cost_{die} = \frac{Cost_{wafer}}{Dies_{per\_wafer} \times Yield}$
- 300mm wafer area: ~70,685 mm².
- Die size 100 mm² → ~600 gross dies per wafer.
- At 90% yield: ~540 good dies.
- 16,000 wafer → ~30 per die at 3nm (before test and packaging).
- Large dies (600+ mm², GPU/AI): ~90 gross dies → after yield, 200-500+ per die.
Cost Scaling Paradox
- Moore's Law historically reduced cost per transistor by ~30% per node.
- At 7nm and below: Cost per transistor INCREASING at some nodes.
- Reason: EUV cost, increased mask layers, more complex process steps.
- Economic response: Chiplet architectures — use advanced nodes only for logic, cheaper nodes for I/O and memory.
Packaging and Test Costs
- Advanced packaging (CoWoS, Foveros): 100-500 per package.
- Test (ATE time at 5-10/minute): 2-20 per die depending on complexity.
- Total chip cost: Die + packaging + test + margin.
Semiconductor economics is the fundamental driver of technology decisions — the escalating cost of leading-edge fabrication is reshaping the industry toward chiplet architectures, heterogeneous integration, and strategic allocation of expensive advanced nodes only where they provide meaningful performance benefits.