Semiconductor Doe

Design of Experiments (DOE) in Semiconductor Process Development is the statistical methodology for efficiently mapping the relationship between process input variables and device output responses — using factorial, central composite, and split-lot experimental designs to characterize process windows, optimize recipes, and identify robust operating points with the minimum number of wafer runs, replacing one-factor-at-a-time (OFAT) experimentation that misses interaction effects and requires 5–10× more experiments.

Why DOE vs OFAT

OFAT (one factor at a time): Vary one parameter while holding others fixed → misses interactions.
Example: Etch rate depends on both pressure AND power, not just each independently.
DOE captures interactions: 2-factor interaction AB → when both A and B are high, response is different than expected from individual effects alone.
Efficiency: Full 2⁵ factorial = 32 runs. 5-factor OFAT = 5×(levels-1) = ~15 runs but misses all interactions.

Full Factorial Design

2-level full factorial: k factors × 2 levels = 2^k runs.
2³ (3 factors): 8 runs → main effects + all 2-way + 1 3-way interaction.
2⁵ (5 factors): 32 runs → impractical for 5-factor optimization → use fractional factorial.

Fractional Factorial Design

2^(k-p) fractional factorial: 2^(5-2) = 8 runs for 5 factors.
Resolution III: Main effects confounded with 2-way interactions → screening only.
Resolution IV: Main effects clear; 2-way interactions confounded with each other → common for process characterization.
Resolution V: All main effects and 2-way interactions estimable → highest quality.
Plackett-Burman: Up to 11 factors in 12 runs → pure screening design.

Central Composite Design (CCD)

Extends 2-level factorial to fit quadratic (Response Surface) model.
Adds: Center point (all factors at midpoint, replicated 3–5×) + star points (axial, at ±α).
Fits: Y = β₀ + Σβᵢxᵢ + Σβᵢᵢxᵢ² + Σβᵢⱼxᵢxⱼ → curved response surface.
Face-centered CCD: α = 1 → star points on face of cube → stays within ±1 range → practical for constrained process.

Split-Lot Wafer Experiment

Semiconductor DOE constraint: Cannot run all process conditions on same wafer.
Split-lot: Divide a lot (25 wafers) into sub-lots → expose each sub-lot to different condition.
Example: Gate oxide DOE — 5 conditions × 5 wafers each = 25-wafer lot fully used.
Hard splits: Some factors can only be split at lot level (e.g., different etch tools, different recipe files).
Soft splits: Factors split within wafer (e.g., different resist doses on different wafer zones — less common).

Response Surface and Process Window

Fit RSM model → visualize contour plots of response (yield, CD, Leakage) vs two factors at a time.
Process window: Region of factor space where all specifications (CD tolerance, yield, leakage) are simultaneously satisfied.
Robust center: Point inside process window maximizing distance from all specification limits → robust to process drift.

Statistical Analysis

import pyDOE2, statsmodels.formula.api as smf, pandas as pd

# 2³ factorial for gate oxide: Temp (T), O2 flow (F), Time (t)
design = pyDOE2.ff2n(3)  # 8-run full factorial
# Map to actual factor levels
df = pd.DataFrame(design, columns=['T', 'F', 't'])
df['T'] = df['T'].map({-1: 900, 1: 1000})   # °C
df['F'] = df['F'].map({-1: 50, 1: 100})    # sccm
df['t'] = df['t'].map({-1: 30, 1: 60})     # seconds
# Run experiments → add measured response
df['tox'] = [3.1, 3.4, 3.2, 3.8, 3.3, 3.6, 3.5, 4.1]  # nm

model = smf.ols('tox ~ T + F + t + T:F + T:t + F:t', data=df).fit()
print(model.summary())

Yield vs Process Variable Screening

Pro-E/Cornerstone (PDF Solutions), JMP (SAS), Minitab: Standard semiconductor DOE tools.
D-optimal designs: Computer-generated designs for constrained factor spaces → when standard designs cannot be run.
Bayesian optimization: ML-guided sequential DOE → select next experiment based on uncertainty model → efficient for high-dim process spaces.

Design of experiments in semiconductor manufacturing is the scientific method applied to silicon — by replacing intuition-guided one-at-a-time tweaking with statistically rigorous multi-factor experiments, DOE enables process teams to characterize 5-dimensional process windows in 16 wafer runs rather than 50, identify interaction effects that would never be discovered through sequential experimentation, and establish truly robust process conditions that remain in-spec across the full manufacturing variability envelope, making DOE the cornerstone methodology that separates world-class process development efficiency from inefficient trial-and-error recipe optimization.

Semiconductor Doe

Take semiconductor doe further