Semiconductor Packaging Wire Bond
Semiconductor Packaging Technology is the post-fabrication discipline that encapsulates bare silicon dies into protected, electrically-connected packages suitable for board-level assembly — where packaging has evolved from simple wire-bond leadframes into a critical performance differentiator, with advanced packaging technologies (flip-chip, fan-out, 2.5D/3D) now accounting for >30% of total chip cost and directly determining the power delivery, signal integrity, thermal performance, and form factor of the final product.
Packaging Evolution
| Generation | Technology | I/O Density | Typical Use |
|---|---|---|---|
| 1st | Wire bond + leadframe | 10-300 pins | Legacy, low-cost ICs |
| 2nd | Wire bond + BGA substrate | 300-2000 pins | Consumer electronics |
| 3rd | Flip-chip + BGA substrate | 2000-10000 bumps | CPUs, GPUs, SoCs |
| 4th | Fan-out WLP (InFO, eWLB) | 500-5000 | Mobile AP, RF |
| 5th | 2.5D/3D (CoWoS, Foveros) | 10000-1M+ | HPC, AI accelerators |
Wire Bonding
Gold or copper wire (15-25 μm diameter) connects die bond pads to package lead fingers. Ball bonding (thermosonic) at 100-200 μm pitch. Still used for >75% of packaged ICs by volume due to low cost. Limitations: wire inductance limits frequency, single-row perimeter I/O.
Flip-Chip
Die is flipped face-down and connected to the substrate through solder bumps across the entire die area (not just the perimeter). Bump pitch: 40-150 μm (C4 bumps) or 10-40 μm (micro-bumps for 2.5D/3D stacking). Benefits: area-array I/O (>10x I/O density vs. wire bond), shorter connections (lower inductance), and direct thermal path from die backside to heatsink.
Fan-Out Wafer/Panel-Level Packaging
Dies are embedded in a reconstituted wafer/panel with RDL (redistribution layers) extending the I/O area beyond the die edge. TSMC InFO powers Apple's A-series and M-series chips. Benefits: thinner profile than flip-chip BGA (important for mobile), no package substrate required (cost reduction), and multi-die integration capability.
Package Substrate
The organic substrate connecting the die (fine pitch) to the PCB (coarse pitch). High-density substrates use 5-15 metal layers with 8-15 μm line/space. ABF (Ajinomoto Build-up Film) dielectric layers provide the low-loss, fine-feature capability. Advanced substrates for HPC (>100mm²) cost $30-100 each — a significant fraction of package cost.
Thermal Management
Package thermal resistance (θJA, θJC) determines the maximum power dissipation:
- Thermal Interface Material (TIM): Connects die to heat spreader. TIM1 (die-to-IHS): indium solder or thermal paste. TIM2 (IHS-to-heatsink): thermal paste.
- Integrated Heat Spreader (IHS): Copper or nickel-plated copper lid soldered to the package substrate, spreading heat from the small die to a larger surface.
- Advanced Cooling: Liquid cooling, vapor chambers, and direct-to-chip cold plates for >300W TDP processors.
Semiconductor Packaging Technology is the critical bridge between the silicon die and the system — transforming a fragile, microscopic chip into a robust, testable, and thermally-manageable component that can be manufactured and assembled at scale.