Sequential 3D Integration

3D IC: go vertical — bond two wafers, or build the second tier in placeParallel 3D bonds finished wafers via TSV or Cu-Cu; monolithic 3D grows a new transistor tier on top, in place1 · Two ways to go verticalParallel — bonddie 2die 1TSV / Cu-Cu bondMonolithic — in placetier 2tier 1inter-tier via (nm)Parallel bonds two finishedwafers; monolithic grows tier 2directly on tier 1 — no bond.Inter-tier vias are far denserthan any bonded connection —that is the whole point.2 · Vertical pitch laddermicrobump~30–40 µmTSV~5–10 µmCu-Cu hybrid bond< 1 µmmonolithic inter-tier via~50–100 nmFiner vertical pitch = finer 3Dpartitioning: whole chips, thenblocks, then individual gates.Bonding buys density; monolithicbuys another 100x on top.3 · Thermal budget & payoffsPayoffsShorter global wiresMemory directly over logicCFET: nFET over pFET, tiny cellsNew floorplans across tiersThe thermal wallTier-2 built cold (<~500 °C) sotier-1 devices surviveBuried tiers are hard to coolYield multiplies across tiersHeat removal and low-temp devicequality are the real limits.Bond or build-in-placeStack and bond two finished wafers,or grow a second transistor tiersequentially on the first.Density sets the payoffFrom TSV µm to monolithic-via nm,finer vertical pitch moves you fromchip-level to gate-level 3D.Heat & thermal budget biteBuried tiers are hard to cool, andmonolithic's top tier must be builtcold enough to spare the bottom.

Sequential 3D Integration (S3D) is a monolithic 3D integration approach that fabricates multiple device layers sequentially on the same wafer — building a second transistor layer directly on top of the first, connected by high-density inter-tier vias, without wafer bonding.

S3D Process

  • Bottom Tier: Fabricate bottom transistors using standard high-temperature processes.
  • Interlayer: Deposit and planarize an interlayer dielectric on top of the bottom tier.
  • Top Tier Channel: Form the top-tier channel by epitaxy, wafer transfer, or laser crystallization.
  • Top Tier Devices: Fabricate top transistors using reduced-temperature processes (≤650°C to protect bottom tier).

Why It Matters

  • Density: Doubles the transistor density per area without shrinking device dimensions.
  • Inter-Tier Vias: Monolithic vias can be ~100 nm diameter (vs. ~1 μm for bonded 3D) — enabling fine-grained connectivity.
  • CFET Enabler: Sequential 3D is the pathway to CFET (complementary FET with NMOS on top of PMOS).

Sequential 3D is stacking transistors one floor at a time — building multiple active device layers monolithically for unprecedented transistor density.

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