SerDes Design
SerDes (Serializer/Deserializer) Design is the high-speed I/O circuit design discipline that converts parallel data into a high-speed serial bit stream for transmission over a single differential pair — achieving data rates from 1 Gbps to 224 Gbps per lane, enabling the PCIe, Ethernet, USB, and chip-to-chip interconnects that provide the bandwidth backbone for all modern computing systems.
Why SerDes?
- Parallel interfaces: N wires × moderate speed → pin-count bottleneck, skew between lanes.
- Serial interface: 1 differential pair × very high speed → fewer pins, no inter-lane skew.
- Example: 32-bit parallel bus at 1 GHz = 32 Gbps on 64 wires. SerDes: 32 Gbps on 2 wires.
SerDes Architecture
| Block | TX (Transmitter) | RX (Receiver) |
|---|---|---|
| Data Path | Serializer (parallel→serial) | Deserializer (serial→parallel) |
| Clocking | PLL (generates bit-rate clock) | CDR (recovers clock from data) |
| Equalization | FFE (Feed-Forward Equalizer) | CTLE + DFE |
| Driver/Receiver | Current-mode driver | Terminated receiver |
| Encoding | 8b/10b, 64b/66b, or PAM4 | Decoder |
SerDes Generations
| Standard | Data Rate/Lane | Encoding | Year |
|---|---|---|---|
| PCIe Gen 3 | 8 GT/s (NRZ) | 128b/130b | 2010 |
| PCIe Gen 5 | 32 GT/s (NRZ) | 128b/130b | 2019 |
| PCIe Gen 6 | 64 GT/s (PAM4) | 256b/257b + FEC | 2022 |
| 100G Ethernet | 25.78 Gbps (NRZ) | 64b/66b | 2015 |
| 400G Ethernet | 106.25 Gbps (PAM4) | RS-FEC | 2020 |
| 800G Ethernet | 106.25 Gbps × 8 | PAM4 + FEC | 2023 |
| UCIe | 32 GT/s (NRZ) | Raw D2D | 2022 |
NRZ vs. PAM4
- NRZ (Non-Return-to-Zero): 2 voltage levels → 1 bit/symbol.
- PAM4: 4 voltage levels → 2 bits/symbol → double the data rate at same baud rate.
- PAM4 penalty: 3x worse SNR than NRZ → requires stronger FEC and equalization.
- Above 56 Gbps: PAM4 is standard (NRZ eye is too closed at these speeds).
Key Design Challenges
- Jitter budget: Total jitter must be < 1 UI (unit interval) → at 112 Gbps PAM4: 1 UI = ~18 ps.
- Channel loss: PCB traces + connectors attenuate signal → 20-40 dB loss at Nyquist frequency.
- Equalization: TX FFE pre-compensates for channel loss. RX CTLE + DFE recovers signal from ISI.
- CDR (Clock and Data Recovery): Extract clock from incoming data — critical for achieving low BER.
- Power: 112G SerDes: 5-10 mW/Gbps → a 400G port (4 lanes) consumes 2-4W.
SerDes design is the enabling technology for all high-bandwidth digital communication — from the PCIe links connecting GPUs to CPUs, to the Ethernet backbone of data centers, to the chip-to-chip links in chiplet architectures, SerDes circuits are the critical I/O interfaces that determine system bandwidth.