Signal Integrity 3D Stacks

# Signal Integrity in 3D Integrated Circuit (3D IC) Stacks

Signal integrity (SI) in 3D integrated circuits is the discipline of preserving electrical waveform fidelity, timing margins, and high-frequency energy transmission across vertical chip-to-chip interconnects. In conventional planar multichip modules, signals propagate laterally across printed circuit board (PCB) traces or silicon interposers over distances of millimeters to centimeters, constrained primarily by dielectric dispersion, trace resistance, and transmission line impedance discontinuities. In 3D IC architectures—such as High Bandwidth Memory (HBM3e/HBM4), 3D V-Cache, and multi-tier heterogeneous logic stacks—interconnect path lengths contract dramatically from millimeters down to tens of micrometers ( $20\text{ to }50\,\mu\text{m}$ ) via Through-Silicon Vias (TSVs), micro-bumps, and direct Cu-Cu hybrid bonding interfaces.

While this vertical compression reduces flight time and absolute interconnect capacitance by orders of magnitude, it introduces severe high-frequency electromagnetic challenges: substrate eddy current losses in conductive bulk silicon ( $\sigma_{Si} \approx 10\,\text{S/m}$ ), dielectric liner capacitive loading ( $C_{TSV} \approx 20\text{ to }80\,\text{fF}$ ), inter-via inductive and capacitive crosstalk ( $$C_m, M$$ ) in ultra-dense TSV arrays, and impedance discontinuities across hybrid bonding interfaces. As data rates scale from 3.2 Gbps NRZ to 32–112 Gbps PAM4, unmitigated 3D vertical interconnects suffer from eye closure, excessive inter-symbol interference (ISI), and catastrophic jitter.

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## 1. High-Frequency Electromagnetic Foundations

Vertical Through-Silicon Vias (TSVs) are cylindrical conductors traversing lossy silicon substrates. Unlike planar transmission lines encased in low-loss dielectrics (e.g., polyimide or low-k silica, $\tan\delta < 0.005$ ), a TSV is directly exposed to conductive bulk silicon ( $\sigma_{Si} \approx 10\,\text{S/m}$ , $\rho_{Si} \approx 10\,\Omega\cdot\text{cm}$ ), establishing a complex Metal-Oxide-Semiconductor (MOS) structure.

### 1.1 Skin Effect & AC Resistance
At direct current (DC), the resistance of a cylindrical TSV of radius $r_{TSV}$ , height $h_{TSV}$ , and copper resistivity $\rho_{Cu} \approx 1.68 \times 10^{-8}\,\Omega\cdot\text{m}$ is:

R_{dc} = \frac{\rho_{Cu} \cdot h_{TSV}}{\pi r_{TSV}^2}

For typical dimensions ( $r_{TSV} = 2.5\,\mu\text{m}$ , $h_{TSV} = 40\,\mu\text{m}$ ), $R_{dc} \approx 34.2\,\text{m}\Omega$ . However, as operating frequency $$f$$ scales into the microwave regime ( $f > 10\,\text{GHz}$ ), alternating currents are expelled from the via core toward its outer perimeter by eddy currents. The electromagnetic skin depth $\delta$ is given by:

\delta = \sqrt{\frac{\rho_{Cu}}{\pi f \mu_0 \mu_r}}

At $f = 28\,\text{GHz}$ (the Nyquist frequency of 56 Gbps NRZ / 112 Gbps PAM4):

\delta = \sqrt{\frac{1.68 \times 10^{-8}}{\pi \cdot (2.8 \times 10^{10}) \cdot (4\pi \times 10^{-7}) \cdot 1.0}} \approx 0.389\,\mu\text{m}

Because $\delta \ll r_{TSV}$ ( $0.39\,\mu\text{m} \ll 2.5\,\mu\text{m}$ ), current flows exclusively within a narrow outer ring, dramatically elevating high-frequency AC resistance:

R_{ac}(f) \approx \frac{\rho_{Cu} \cdot h_{TSV}}{2 \pi r_{TSV} \cdot \delta} = \frac{h_{TSV}}{2 r_{TSV}} \sqrt{\frac{\rho_{Cu} \mu_0 f}{\pi}} \propto \sqrt{f}

At 28 GHz, $R_{ac} \approx 0.11\,\Omega$ , more than three times its DC value, contributing to severe high-frequency attenuation.

### 1.2 Non-Linear MOS Depletion & Liner Capacitance
A thin dielectric isolation liner (typically chemical vapor deposited $\text{SiO}_2$ , $t_{ox} \approx 100\text{ to }200\,\text{nm}$ , $\epsilon_{ox} \approx 3.9$ ) surrounds the copper cylinder to prevent copper diffusion into silicon. The dielectric liner capacitance $C_{ox}$ is:

C_{ox} = \frac{2 \pi \epsilon_0 \epsilon_{ox} h_{TSV}}{\ln\left(1 + \frac{t_{ox}}{r_{TSV}}\right)}

For $r_{TSV} = 2.5\,\mu\text{m}$ , $t_{ox} = 150\,\text{nm}$ , and $h_{TSV} = 40\,\mu\text{m}$ :

C_{ox} \approx \frac{2\pi \cdot (8.854 \times 10^{-12}) \cdot 3.9 \cdot (40 \times 10^{-6})}{\ln(1 + 0.15 / 2.5)} \approx \frac{8.67 \times 10^{-15}}{0.0583} \approx 148.8\,\text{fF}

Because the silicon substrate is moderately doped with p-type impurities, applied signal voltages establish a space-charge depletion layer of width $w_{dep}$ in the silicon surrounding the oxide:

C_{dep}(V) = \frac{2 \pi \epsilon_0 \epsilon_{Si} h_{TSV}}{\ln\left(1 + \frac{w_{dep}(V)}{r_{TSV} + t_{ox}}\right)}

The effective high-frequency TSV capacitance is the series combination of oxide liner capacitance and voltage-dependent depletion capacitance:

C_{TSV}(V) = \frac{C_{ox} \cdot C_{dep}(V)}{C_{ox} + C_{dep}(V)}

Under high-frequency AC excitation, $C_{TSV}$ stabilizes between $25\text{ to }60\,\text{fF}$ . This lump capacitance forms a low-pass filter with driver impedance, capping signal bandwidth unless compensated.

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## 2. Quantitative Modeling: S-Parameters, Crosstalk & Eye Diagrams

### 2.1 Inter-Via Capacitive and Inductive Crosstalk
In dense 3D vertical interconnect fabrics, mutual capacitance $$C_m$$ and mutual inductance $$M$$ between adjacent TSVs cause severe electromagnetic crosstalk. Consider two parallel cylindrical TSVs separated by center-to-center pitch $$s$$ . The mutual capacitance through silicon is:

C_m \approx \frac{\pi \epsilon_0 \epsilon_{Si} h_{TSV}}{\ln\left( \frac{s}{2 r_{TSV}} + \sqrt{\left(\frac{s}{2 r_{TSV}}\right)^2 - 1} \right)}

The mutual inductance through the magnetic field in silicon is:

M \approx \frac{\mu_0 h_{TSV}}{2\pi} \left[ \ln\left( \frac{h_{TSV}}{s} + \sqrt{1 + \left(\frac{h_{TSV}}{s}\right)^2} \right) - \sqrt{1 + \left(\frac{s}{h_{TSV}}\right)^2} + \frac{s}{h_{TSV}} \right]

For an unshielded aggressive pitch ( $s = 10\,\mu\text{m}$ , $r_{TSV} = 2.5\,\mu\text{m}$ , $h_{TSV} = 40\,\mu\text{m}$ ), $C_m \approx 18\text{ to }25\,\text{fF}$ and $M \approx 12\text{ to }18\,\text{pH}$ . When an aggressor net switches with a high slew rate ( $dV/dt \ge 1.0\,\text{V/ps}$ ):

I_{crosstalk} = C_m \frac{dV_{aggressor}}{dt} \approx (20 \times 10^{-15}) \cdot (1.0 \times 10^{12}) \approx 20\,\text{mA}

This transient displacement current injects directly into adjacent victim lines through the conductive silicon substrate, causing false logic transitions and jitter.

The Far-End Crosstalk (FEXT) transfer coefficient $K_{FEXT}$ across an electrical length $t_{flight}$ with signal rise time $t_{rise}$ is governed by:

K_{FEXT} = \frac{1}{2} \left( \frac{C_m}{C_{total}} - \frac{M}{L_{total}} \right) \cdot \frac{t_{flight}}{t_{rise}}

In unshielded arrays, $K_{FEXT}$ reaches $-12\text{ to }-15\,\text{dB}$ at 20 GHz, which completely closes the eye diagram in high-speed PAM4 links.

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## 3. Engineering Mitigations: Shielding, Matching & Hybrid Interconnects

Semiconductor architects deploy four rigorous design rules to maintain signal integrity in leading-edge 3D stacks:

### 3.1 Ground-Signal-Ground (G-S-G) Shielding Lattices
In single-ended signaling, surrounding each signal TSV with dedicated Ground (GND) or Power ( $V_{DD}$ ) return TSVs creates a virtual coaxial shield.
1. Coaxial Isolation: The electric field lines emanating from the signal via terminate on adjacent ground vias rather than penetrating the lossy substrate to victim lines.
2. Current Loop Area Minimization: The return current path directly mirrors the signal path, collapsing the magnetic loop area $A_{loop}$ and reducing effective loop inductance $L_{loop}$ from $>60\,\text{pH}$ down to $<15\,\text{pH}$ .
3. Crosstalk Suppression: A fully surrounded G-S-G or hexagonal shield grid suppresses FEXT to below $-35\,\text{dB}$ at frequencies exceeding 40 GHz.

### 3.2 Characteristic Impedance Matching ( $Z_0 \approx 50\,\Omega$ )
A standalone TSV has an intrinsic characteristic impedance $$Z_0$$ :

Z_0 = \sqrt{\frac{R_{ac} + j\omega L_{TSV}}{G_{Si} + j\omega C_{TSV}}}

Because of the high capacitance ( $C_{TSV} \approx 60\,\text{fF}$ ) and small height ( $h \approx 40\,\mu\text{m}$ ), an un-optimized TSV exhibits a very low impedance ( $Z_0 \approx 20\text{ to }30\,\Omega$ ), creating a severe impedance discontinuity against standard $50\,\Omega$ on-die transmission lines. This discontinuity induces substantial return loss ( $S_{11} > -10\,\text{dB}$ ):

\Gamma = \frac{Z_{TSV} - Z_0}{Z_{TSV} + Z_0}

To achieve impedance matching to $50\,\Omega$ :
- Thicker Oxide Liners: Increasing $t_{ox}$ from $100\,\text{nm}$ to $300\text{ to }400\,\text{nm}$ lowers $C_{ox}$ .
- Air-Gap or Low-k Liners: Replacing $\text{SiO}_2$ with low-k polymers or conformal dielectric barriers ( $\epsilon_r \approx 2.5$ ) reduces unit capacitance.
- Pitch Optimization: Tuning the signal-to-ground spacing $$s$$ balances $$L/C$$ to match $50\,\Omega$ single-ended or $100\,\Omega$ differential.

### 3.3 Micro-Bump vs. Direct Hybrid Bonding Parasitics
The transition from micro-bump flip-chip to direct Cu-Cu hybrid bonding represents a major signal integrity leap:

+----------------------------------------------------------------------------------------------------+
|                                INTERCONNECT PARASITIC COMPARISON                                   |
+----------------------+-----------------------------+-----------------------+-----------------------+
| METRIC               | SOLDER MICRO-BUMP (25 µm)   | FINE-PITCH BUMP (10µm)| DIRECT HYBRID BONDING |
+----------------------+-----------------------------+-----------------------+-----------------------+
| Interconnect Form    | Cu Pillar + Sn-Ag solder    | Micro-pillar + cap    | Atomic Cu-Cu direct   |
+----------------------+-----------------------------+-----------------------+-----------------------+
| Standoff Height (h)  | 10 µm to 15 µm              | 3 µm to 5 µm          | 0 µm (Direct seal)    |
+----------------------+-----------------------------+-----------------------+-----------------------+
| Interconnect Pitch   | 25 µm to 40 µm              | 10 µm to 15 µm        | 0.5 µm to 3.0 µm      |
+----------------------+-----------------------------+-----------------------+-----------------------+
| Lumped Resistance    | 15 mΩ to 30 mΩ              | 25 mΩ to 45 mΩ        | <2 mΩ to 5 mΩ         |
+----------------------+-----------------------------+-----------------------+-----------------------+
| Parasitic Capacitance| 15 fF to 35 fF              | 6 fF to 12 fF         | <0.5 fF to 1.0 fF     |
+----------------------+-----------------------------+-----------------------+-----------------------+
| Parasitic Inductance | 20 pH to 40 pH              | 8 pH to 15 pH         | <2 pH                 |
+----------------------+-----------------------------+-----------------------+-----------------------+
| Bandwidth (-1 dB)    | ~15 GHz                     | ~35 GHz               | >100 GHz (Terahertz)  |
+----------------------+-----------------------------+-----------------------+-----------------------+

Direct hybrid bonding eliminates the capacitive solder barrel stub, extending linear transmission bandwidth beyond 100 GHz and allowing multi-terabit/s memory and compute interfaces without complex receiver equalization.

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## 4. Power Integrity Coupling: Simultaneous Switching Noise (SSN)

Signal integrity in 3D stacks cannot be separated from power integrity (PI). When hundreds of vertical I/O channels switch simultaneously, high-speed transient current demand $\sum dI/dt$ draws current through the finite loop inductance $L_{PDN}$ of the vertical Power Delivery Network:

\Delta V_{SSN} = L_{PDN} \frac{dI_{total}}{dt} = L_{PDN} \sum_{k=1}^N \frac{dI_k}{dt}

This voltage perturbation (ground bounce and power droop) directly modulates the reference voltage of single-ended receivers. In a 3D memory stack (e.g., 1024-bit wide HBM bus), if 256 data lines switch within 50 ps ( $dI/dt \approx 50\,\text{A/ns}$ ), an effective power TSV inductance of only $10\,\text{pH}$ produces:

\Delta V_{SSN} = (10 \times 10^{-12}\,\text{H}) \cdot (50 \times 10^9\,\text{A/s}) = 0.50\,\text{V}

In a 1.0 V supply domain, a 0.50 V bounce causes instantaneous bit errors. To suppress SSN:
1. On-Die Deep Trench Capacitors (DTC): High-density silicon trench capacitors ( $>100\,\text{nF/mm}^2$ ) are embedded within the active silicon tiers directly adjacent to power TSVs.
2. Dedicated Power/Ground TSV Ratios: High-speed 3D buses enforce a 1:1 or 1:2 ratio of signal TSVs to power/ground TSVs, providing low-inductance vertical charge reservoirs.

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## 5. Technology Comparison: 3D High-Speed Signaling Standards

+----------------------------------------------------------------------------------------------------+
|                               COMPARATIVE MATRIX OF 3D SIGNALING ARCHITECTURES                     |
+----------------------+---------------------+-----------------------+-------------------------------+
| PARAMETER            | HBM3e (MICRO-BUMP)  | UCIe 3D (HYBRID BOND) | TSMC SoIC (DIRECT HYBRID)     |
+----------------------+---------------------+-----------------------+-------------------------------+
| Signaling Topology   | Single-Ended NRZ    | Single-Ended & Diff   | High-Speed Core-to-Core Direct|
+----------------------+---------------------+-----------------------+-------------------------------+
| Data Rate per Pin    | 9.6 Gbps            | 16.0 to 32.0 Gbps     | >50.0 Gbps (PAM4 Capable)     |
+----------------------+---------------------+-----------------------+-------------------------------+
| Bus Width            | 1024-bit per stack  | Modular (x64 to x512) | Dense Matrix Array (>10,000)  |
+----------------------+---------------------+-----------------------+-------------------------------+
| Interconnect Pitch   | 25 µm to 35 µm      | 1.0 µm to 9.0 µm      | 0.5 µm to 1.8 µm              |
+----------------------+---------------------+-----------------------+-------------------------------+
| Reach / Flight Length| 40 µm to 350 µm     | 20 µm to 100 µm       | <20 µm                        |
+----------------------+---------------------+-----------------------+-------------------------------+
| Energy Efficiency    | 3.0 to 5.0 pJ/bit   | <0.25 to 0.5 pJ/bit   | <0.05 pJ/bit (Sub-pJ Class)   |
+----------------------+---------------------+-----------------------+-------------------------------+
| Bandwidth Density    | ~1.2 TB/s per stack | >10 TB/s/mm²          | >30 TB/s/mm²                  |
+----------------------+---------------------+-----------------------+-------------------------------+
| Primary Limitation   | Underfill thermal / | TSV placement overlay | Substrate noise isolation /   |
|                      | bump capacitance    | accuracy (<150 nm)    | power distribution resonance  |
+----------------------+---------------------+-----------------------+-------------------------------+

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