Smt Hyperthreading
Simultaneous Multithreading (SMT / Hyper-Threading) is the CPU hardware technique of executing instructions from multiple software threads on a single physical core in the same clock cycle — sharing the core's execution units, caches, and functional resources between 2-8 hardware threads to improve utilization of otherwise-idle resources, typically increasing throughput by 20-30% with near-zero additional silicon area.
How SMT Works
- A single physical core has multiple execution units (ALUs, load/store units, FP units).
- Single-threaded: Many execution slots go unused each cycle — pipeline bubbles from branch mispredicts, cache misses, data dependencies.
- SMT: When Thread A stalls (cache miss), Thread B's instructions fill the empty slots.
- Each hardware thread has its own: program counter, register file, TLB entries.
- Shared between threads: execution units, cache, branch predictor, memory subsystem.
SMT Implementations
| Processor | SMT Width | Threads/Core | Name |
|---|---|---|---|
| Intel Core (most) | 2-way | 2 | Hyper-Threading (HT) |
| Intel Xeon (some) | 2-way | 2 | Hyper-Threading |
| AMD Zen 1-5 | 2-way | 2 | SMT |
| IBM POWER9 | 4/8-way | 4 or 8 | SMT4/SMT8 |
| Oracle SPARC M8 | 8-way | 8 | |
| ARM (most) | None | 1 | No SMT in most ARM designs |
Performance Impact
| Workload Type | SMT Benefit | Why |
|---|---|---|
| Memory-bound server | +25-40% | Thread A stalls on cache miss, Thread B fills pipeline |
| Compute-bound (math) | +5-15% | Both threads compete for the same ALUs |
| Latency-sensitive | Variable | May hurt latency of individual threads |
| HPC (vectorized) | 0 to -5% | Threads compete for vector units — sometimes slower |
SMT Concerns
- Security: SMT enables side-channel attacks (Spectre, MDS) — shared execution resources leak information between threads.
- Mitigations: Disable HT for sensitive workloads, kernel process isolation.
- Interference: Two threads sharing L1 cache → more evictions → individual thread performance decreases.
- Scheduling: OS must be SMT-aware — don't spread two threads of the same process to different physical cores if same core has idle SMT slot.
When to Disable SMT
- Real-time latency-critical systems (consistent single-thread performance needed).
- Security-sensitive environments (secrets in memory shared with untrusted threads).
- Workloads already fully utilizing all execution units (dense compute).
SMT is one of the most cost-effective ways to improve CPU throughput — by adding only 5-10% more silicon area for duplicated thread state, it extracts 20-30% more useful work from the expensive execution resources that would otherwise sit idle during pipeline stalls.