Spacer Formation

Spacer formation deposits and etches insulating material onto the sidewalls of an already-formed gate stack, creating the precisely controlled offset between the gate edge and the subsequent deep source/drain implant — one of the most tightly controlled dimensions anywhere in the transistor process, because that spacer width directly determines overlap capacitance, series resistance, and short-channel behavior all at once. Beyond its role in individual transistor formation, spacer technology has taken on an entirely second life as the actual patterning mechanism behind self-aligned double patterning, making spacer formation one of the rare process steps that matters just as much for lithography as it does for transistor structure.

The LDD-then-spacer-then-heavy-implant sequence exists specifically to create two distinct doping regions with two different purposes: a light drain extension implant placed before the spacer forms the gradual, low-field region right at the channel edge, while the heavier source/drain implant placed after the spacer forms farther from the gate edge, offset by exactly the spacer's own width. This sequencing is exactly what gives transistor designers independent control over two genuinely different electrical requirements — a lightly doped extension tuned to manage electric field and hot-carrier effects right at the channel edge, and a heavily doped bulk source/drain region tuned to minimize series resistance — using the spacer's physical width as the parameter separating where one ends and the other begins.

Anisotropic dry etching, with vertical etch rate dramatically exceeding lateral etch rate, is the specific mechanism that converts a uniform, conformally deposited film into a sidewall-only spacer, because that etch directionality clears film from every horizontal surface while leaving the vertical sidewall surfaces essentially untouched. This directional etch selectivity is the entire reason spacer formation works at all — a purely isotropic etch would remove material from horizontal and vertical surfaces at comparable rates, eroding the sidewall film right alongside the horizontal film it's actually meant to clear, which would leave no usable spacer behind regardless of how the deposition step itself was controlled.

Single, dual, and triple spacer architectures represent genuinely increasing process sophistication rather than arbitrary stylistic variation: single spacers suited older, simpler nodes; dual spacers (an oxide liner plus a nitride spacer) give meaningfully better dimensional control and became the standard approach; triple spacers support the multiple distinct implant offsets and the self-aligned contact requirements that advanced nodes specifically demand. This escalating spacer complexity directly tracks the escalating number of independent offset distances a modern transistor actually needs — more implant steps requiring more precisely different offsets simply can't be achieved with a single spacer layer, which is exactly why spacer architecture complexity has grown in lockstep with the number of distinct implant and contact-protection functions a single transistor's spacer stack now has to serve.

Self-aligned double patterning (SADP) repurposes spacer-formation technology entirely for lithography rather than for transistor structure, by depositing a conformal film around a sacrificial mandrel pattern, etching it with the same anisotropic process used for transistor spacers, then removing the mandrel so that only the spacer itself remains as the actual patterning mask. This repurposing is exactly how SADP achieves feature pitches finer than what the original lithography exposure alone could resolve — the spacer's own width, controlled by deposition thickness rather than by lithographic exposure, becomes the limiting dimension, converting a deposition-and-etch process into a genuine sub-lithographic patterning technique.

Spacer width — typically specified in the 10 to 30 nanometer range — simultaneously controls transistor overlap capacitance, series resistance, and short-channel behavior, which is exactly why it ranks among the most tightly controlled single dimensions in the entire transistor process rather than being treated as a secondary parameter. A wider spacer reduces overlap capacitance and improves short-channel behavior but increases series resistance by pushing the heavy source/drain implant further from the channel; a narrower spacer does the opposite — this is a genuine three-way tradeoff with no dimension that simultaneously optimizes all three properties, which is exactly why spacer width gets specified and controlled as precisely as any other critical transistor dimension in the process.