SRAM Bitcell Design Custom

The 6T SRAM cell: two inverters that hold one bit by fighting each otherCross-coupled inverters latch the bit; two access transistors let the bitlines read or write it1 · Six transistorsa latch plus two gatesWL (wordline)BLBL̄M5M6INVAINVBQQ̄4 latch FETs (M1–M4) + 2 access (M5,M6)Q and Q̄ always hold opposite valuesTwo inverters wired output-to-inputform a latch with two stable states.2 · Read & writethe wordline opens the doorHold (WL = 0)access FETs off; the latch feeds backon itself and keeps the bit forever— as long as the cell stays powered.static: no refresh needed.Read (WL = 1)precharge both bitlines high, raise WL;the storage node pulls one BL down alittle; a sense amp resolves the bit.Write (WL = 1)drive the bitlines hard to the new value;the access FETs overpower the latch andflip Q / Q̄ to the written state.3 · Why SRAM, and its costfast and stable, but bigFast & staticsingle-cycle access, no refresh — idealfor caches right next to the cores.Six transistors = areafar larger per bit than DRAM’s 1T1C,so capacity is limited & expensive.Stability marginsread must not disturb the bit; sizingratios set read/write noise margins.The bitcell sets the SoCSRAM is often half a modern chip’s area.Foundries push a specially-drawn cell tothe density limit each node; it drivescache size, cost and yield.Cross-coupled latchTwo inverters hold Q and Q̄ — thebit is stored as a stable state.Access transistorsThe wordline gates the bitlines ontothe node to read or write.Static, not stored chargeHolds its bit with no refresh — butat six transistors per bit.

Custom SRAM Bitcell Design is the foundational circuit design discipline focused on optimizing the 6-transistor (6T) memory cell for stability, performance, and density at advanced technology nodes — where read stability, write margin, hold margin, and cell area present tightly coupled design trade-offs that define the memory's yield and performance.

6T SRAM Cell Architecture:
- Cross-Coupled Inverters: two CMOS inverters (NMOS pull-down + PMOS pull-up) connected in positive feedback loop store one bit — bistable latch maintains state as long as supply voltage exceeds minimum retention voltage (VMIN)
- Access Transistors: two NMOS pass-gate transistors connect storage nodes to bit-lines during read/write — gate driven by word-line; access transistor sizing critically balances read and write operations
- Cell Ratio (CR): ratio of pull-down NMOS width to access NMOS width — CR > 1.5 required for read stability (pull-down must overpower access transistor during read to prevent flip)
- Pull-Up Ratio (PR): ratio of access NMOS width to pull-up PMOS width — PR > 1.2 required for writability (access transistor must overpower pull-up PMOS to force new data into cell)

Read Operation and Stability:
- Read Mechanism: word-line assertion connects storage nodes to pre-charged bit-lines through access transistors — cell storing '0' discharges one bit-line through series access-NMOS and pull-down-NMOS, creating differential voltage sensed by sense amplifier
- Read Disturb: during read, the '0' storage node rises from VSS due to voltage divider between access and pull-down transistors — if this voltage exceeds the switching threshold of the feedback inverter, the cell flips (destructive read)
- Static Noise Margin (SNM): measured as the maximum DC noise voltage that the cell can tolerate without flipping during read — graphically determined as the largest square inscribed in the butterfly curve of the cross-coupled inverters
- Read SNM Scaling: SNM degrades with technology scaling due to increased Vt variation (RDF), reduced voltage headroom, and higher leakage — 6T cells at 7 nm and below require assist techniques to maintain acceptable read SNM

Write Operation and Margin:
- Write Mechanism: one bit-line driven low while word-line is asserted — access transistor overpowers the pull-up PMOS to force the '1' node to '0', triggering the cross-coupled latch to flip to the new state
- Write Margin: measured as the minimum bit-line voltage required to flip the cell — insufficient write margin causes write failures where the cell retains its old value
- Write Assist Techniques: negative bit-line voltage (NBL) enhances pass transistor drive; word-line boosting increases access transistor gate overdrive; supply voltage collapse weakens pull-up PMOS — each technique trades reliability margin for improved writability

Scaling Challenges:
- Variability: random dopant fluctuation at sub-10 nm nodes causes Vt variation of 30-50 mV between adjacent transistors — 6-sigma design margin requires cells functional across wide Vt distribution
- Cell Area: drive for smallest possible cell (0.025-0.05 μm² at 5 nm) conflicts with need for larger transistors to maintain margins — cell area directly determines SRAM macro density and chip cost
- Leakage: sub-threshold leakage increases exponentially with scaling — half-select leakage in unaccessed cells on the same word-line or bit-line contributes to power consumption and read/write disturb

Custom SRAM bitcell design is the most critical circuit-level enabler of semiconductor memory density — the bitcell's stability margins, noise immunity, and variability tolerance directly determine the maximum memory capacity achievable at each process node and define the yield structure of the entire chip.

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