Timing Signoff
Timing Signoff is the final verification step that confirms all timing paths in the chip meet their setup, hold, and transition time requirements across all operating conditions — the last gate before tapeout authorization, where failure to close timing means the chip will either not function at the target frequency or produce incorrect results.
What Timing Signoff Checks
- Setup time: Data arrives before clock edge with sufficient margin.
- Hold time: Data stable for sufficient time after clock edge.
- Transition time (slew): Signal edges not too slow (causes power waste) or undefined (causes metastability).
- Clock skew/uncertainty: Clock arrives at different times to different flops.
- Noise/Crosstalk: Signal integrity effects that can accelerate or delay transitions.
Signoff Corners
| Corner | Voltage | Temperature | Process | Checks |
|---|---|---|---|---|
| Worst-case slow (SS) | Low V | High T | Slow | Setup (slow paths) |
| Worst-case fast (FF) | High V | Low T | Fast | Hold (fast paths) |
| Typical (TT) | Nominal | 25°C | Typical | Nominal performance |
| Best-case fast (FF cold) | High V | -40°C | Fast | Hold (extreme) |
- Multi-Corner Multi-Mode (MCMM): Every operating mode (active, sleep, turbo) × every PVT corner.
- Typical signoff: 20-50+ corner-mode combinations.
Signoff Tools
- PrimeTime (Synopsys): Industry gold standard for static timing analysis signoff.
- Tempus (Cadence): Competing STA signoff tool.
- PTSI (PrimeTime with Signal Integrity): Includes crosstalk impact on timing.
Signoff Flow
1. Extract parasitics: StarRC or QRC extracts R and C from physical layout.
2. Run STA: PrimeTime/Tempus analyzes all paths across all corners.
3. Fix violations: ECO (Engineering Change Order) to fix failing paths — buffer insertion, cell resizing, routing changes.
4. Re-extract and re-analyze: Iterate until all violations closed.
5. Generate reports: WNS (worst negative slack), TNS (total negative slack), max transition violations.
6. Signoff review: Lead engineer reviews reports and authorizes tapeout.
Signoff Criteria
- WNS ≥ 0 ps (no negative slack) across ALL corners and modes.
- Max transition: All signals within library limits.
- Clock domain crossing: All CDC paths properly constrained.
- Zero DRC violations in timing reports.
Timing signoff is the most critical pre-tapeout verification step — a missed timing violation that reaches silicon means the chip either fails to meet its frequency target (reducing market value) or produces incorrect computations (requiring a mask respin costing $10-50M+).