Tungsten Plug Process
Tungsten Plug Process is the CVD-based contact fill technique that deposits tungsten metal into high-aspect-ratio contact holes to form the vertical connections between transistor terminals and the first metal layer — where the nucleation, growth, and fill properties of the tungsten film determine the contact resistance, void-free fill quality, and ultimately the performance of every transistor in the circuit.
Why Tungsten for Contacts?
- Excellent CVD conformality — fills high-AR holes (> 10:1) without voids.
- Refractory metal: Withstands subsequent thermal processing (up to 400-500°C).
- Low resistivity: ~5 μΩ·cm (thin film) — higher than Cu but acceptable for short plugs.
- No diffusion into silicon: Unlike Cu, W does not poison transistor junctions.
W CVD Process Flow
1. Contact etch: Etch contact holes through ILD0 to expose S/D silicide or gate.
2. Barrier deposition: PVD Ti (adhesion, ~5 nm) + CVD TiN (barrier, ~5 nm).
3. W nucleation: Thin W seed layer from WF6 + SiH4 (silane reduction).
4. W bulk fill: Thick W from WF6 + H2 reduction fills the contact hole.
5. W CMP: Polish back excess W — leaves W plugs flush with ILD surface.
W CVD Chemistry
| Step | Reaction | Temperature |
|---|---|---|
| Nucleation | WF6 + SiH4 → W + SiF4 + H2 | 300-350°C |
| Bulk Fill | WF6 + 3H2 → W + 6HF | 350-400°C |
- SiH4 nucleation: Forms initial W seed on TiN barrier — low-fluorine process.
- H2 reduction: Standard bulk fill — higher deposition rate but requires good nucleation layer.
- B2H6 nucleation: Alternative using diborane — used for some advanced processes.
Contact Resistance
- Total Rc = R_silicide + R_barrier + R_W_plug + R_interface.
- Silicide-to-silicon contact dominates: ~10⁻⁸ to 10⁻⁹ Ω·cm².
- W plug resistance: For a 20 nm diameter, 50 nm tall plug: ~50-100 Ω.
- At advanced nodes: Contact resistance is a significant fraction of total parasitic R.
Challenges at Advanced Nodes
- Extreme AR: 3nm node contacts: AR > 15:1 with diameter < 15 nm.
- Barrier thickness overhead: Ti/TiN eats into the plug volume — less room for W.
- Fluorine attack: WF6 can etch the TiN barrier if nucleation is poor → reliability risk.
- Alternatives emerging: Cobalt (Co) and Ruthenium (Ru) contacts for sub-5nm nodes — lower barrier-thickness overhead.
The tungsten plug process is one of the most critical integration steps in CMOS manufacturing — it forms the first metal-to-silicon connection that every transistor signal must pass through, making contact resistance and fill quality direct limiters of chip speed and yield.