UCIe

UCIe (Universal Chiplet Interconnect Express) is an open industry standard for connecting chiplets — separate silicon dies — together inside a single package. As monolithic chips hit the limits of what one die can economically contain, designers increasingly build a product from several smaller dies (a CPU die, an accelerator die, an I/O die, memory) placed side by side and wired together. UCIe standardizes that die-to-die link the way PCIe standardized board-level I/O, so that dies from different vendors and different process nodes can be mixed and matched in one package. It is the interconnect meant to turn chiplets from a proprietary, one-vendor trick into an open ecosystem.

The problem it solves is that die-to-die links were all proprietary. AMD's Infinity Fabric, Intel's AIB/EMIB links, and NVIDIA's NVLink-C2C each let a company stitch its own dies together, but a chiplet built for one could not plug into another. UCIe defines a common physical interface, protocol, and software model so a die that speaks UCIe can interoperate with any other UCIe die, enabling a marketplace where you buy a best-in-class I/O chiplet from one vendor and pair it with a compute chiplet from another.

It is layered like PCIe, and deliberately reuses PCIe/CXL on top. The physical layer defines the bumps, lanes, clocking, and a sideband channel. The die-to-die adapter handles link state management, CRC, retries, and arbitration for reliability. The protocol layer maps established protocols — PCIe and CXL — over the link, plus a raw "streaming" mode for anything else. Because the upper layers are just PCIe and CXL, existing software and IP work across a chiplet boundary with little change.

Two package classes trade reach against density. A standard package routes UCIe over an ordinary organic substrate: cheaper, longer reach (roughly 10–25 mm), but wider bump pitch and lower bandwidth density. An advanced package uses a silicon interposer or bridge (2.5D integration like CoWoS or EMIB) with very fine bump pitch: short reach (a couple of millimeters) but enormous bandwidth density and better energy per bit. The same UCIe stack runs on both; you pick the package for your cost and bandwidth targets.

The figures of merit are bandwidth density and energy per bit, not just raw speed. Because a die has only so much edge and area to place bumps, what matters is how much bandwidth you get per millimeter of die edge (or per mm²) and how few picojoules each bit costs. Advanced-package UCIe targets sub-0.5 pJ/bit and very high bandwidth per millimeter, with die-to-die latency under a couple of nanoseconds — numbers that make crossing a chiplet boundary feel almost like staying on-die.

It is foundational to modern AI silicon. Large accelerators are already multi-die, and the economics of splitting a big design into yield-friendly chiplets — mixing process nodes, reusing I/O dies, scaling compute independently — only work if the interconnect between dies is fast, cheap, and standard. UCIe is the open bet on that future: it lets the industry build ever-larger "virtual" chips out of composable dies without every vendor reinventing the link.

Read UCIe through a *composable-die-ecosystem* lens rather than a *just-another-bus* lens: the point is not a single fast wire but a standard that lets dies from different vendors and process nodes snap together inside one package. Once the die-to-die link is open and cheap enough that crossing it costs almost nothing, a "chip" becomes a configuration of chiplets you assemble — and that is exactly how the largest AI processors are now being built.