Voltage Droop
Voltage Droop and Power Supply Noise is the transient voltage reduction on the chip's internal power grid that occurs when circuit switching activity changes suddenly — caused by the di/dt (rate of current change) through the parasitic inductance of the power delivery network (PDN) from the voltage regulator through the package to the die, where a typical droop of 50-100mV on a 0.75V supply (7-13%) directly reduces transistor drive current and can cause timing violations or logic errors if not properly mitigated.
Droop Physics
- Ohm's law: V_droop = L × di/dt + R × I
- L = total inductance (package pins + planes + on-die) ≈ 10-100 pH.
- di/dt: Sudden current change when many circuits switch simultaneously.
- Example: 100A current spike in 1ns through 50pH → V = 50pH × 100A/1ns = 5V!
- In practice: Distributed L and C filter the spike → droop is 50-150mV, lasting 10-100ns.
Droop Events
| Event | Current Change | Droop Magnitude | Duration |
|---|---|---|---|
| Cache miss → execute | 10-30A in 5ns | 50-100mV | 10-50ns |
| SIMD burst start | 20-50A in 2ns | 80-150mV | 20-100ns |
| Clock ungating (full core) | 15-40A in 1ns | 100-200mV | 30-100ns |
| Power gate wake-up | 30-80A in 10ns | 100-200mV | 50-200ns |
PDN Impedance Target
Z_target = V_supply × ripple% / I_max
Example: 0.75V supply, 5% allowed ripple, 100A max current
Z_target = 0.75 × 0.05 / 100 = 375 µΩ
This impedance must be maintained from DC to ~1GHz!PDN Structure
- Each level handles different frequency range of current transients.
- Board capacitors: Handle slow transients (µs).
- Package decaps: Handle medium-speed transients (10-100ns).
- On-die decaps: Handle fast transients (1-10ns) — most critical for droop.
Droop Mitigation Strategies
| Strategy | Level | Effectiveness | Cost |
|---|---|---|---|
| On-die decoupling capacitors | Die | Absorb ~1ns transients | Die area |
| Package decoupling capacitors | Package | Absorb ~10ns transients | Package cost |
| Wider power grid (lower R) | Die | Reduce resistive IR drop | Routing resources |
| Staggered clock gating | Design | Spread di/dt over time | Design complexity |
| Current sensor + throttle | Design | Limit peak di/dt | Performance loss |
| On-chip IVR | Die | Fast voltage regulation | Area + power |
| Backside power delivery | Die + Pkg | 50% reduction in PDN impedance | Advanced process |
Guardband Impact
- Design must work at V_min = V_supply - V_droop.
- 100mV droop on 750mV supply → design for 650mV → ~15% frequency loss.
- Reducing droop by 50mV → raise frequency by ~8% → significant performance gain.
- Every mV of droop reduction translates directly to performance or power savings.
Simulation and Signoff
- Dynamic IR drop analysis: Simulate power grid with time-varying current.
- Tools: Ansys RedHawk-SC, Cadence Voltus → compute worst-case droop at every node.
- VCD-based: Use simulation vectors → realistic switching patterns → accurate droop prediction.
- Vectorless: Statistical estimation → faster but conservative.
Voltage droop is the invisible performance thief in modern processor design — the guardbands that designers add to handle worst-case droop events directly subtract from achievable frequency, making PDN design and droop mitigation one of the highest-leverage optimizations for high-performance chips, where reducing voltage droop by even 10-20mV through better decoupling, power delivery, and di/dt management translates directly into measurable frequency and power efficiency improvements.