What Is a Spacer Semiconductor

A spacer is a thin sidewall of insulating material formed against the edges of a transistor's gate, and it exists to precisely control where the source and drain regions begin relative to the gate — a positioning problem that would otherwise be nearly impossible to solve directly. After the gate structure covered in the FinFET/GAA discussion is formed, the transistor still needs source and drain regions implanted on either side of it, and exactly how close those regions sit to the gate edge has an enormous effect on transistor performance: too close and the gate can't turn the channel off properly (excess leakage); too far and the transistor is slower than it needs to be. Rather than trying to align an implant mask to the gate edge with impossible precision, engineers deposit a conformal layer of insulating material over the whole gate structure, then etch it back so that only the material clinging to the near-vertical gate sidewalls survives — automatically self-aligned to the gate's actual position, however that gate ended up shaped after its own litho and etch steps.

This self-alignment trick is exactly why spacers are formed the way they are, and it depends directly on techniques covered earlier in this series. A conformal CVD or ALD process — the same conformality requirement described when covering CVD earlier, and again when covering how GAA nanosheets need every side of a suspended channel coated evenly — deposits an even layer of insulating material across the entire gate structure, coating the top, the sidewalls, and the surrounding flat silicon all at a similar thickness. An anisotropic plasma etch then removes material preferentially from flat horizontal surfaces while leaving the vertical sidewall material largely intact, because the etch's directional ion bombardment attacks horizontal surfaces far more aggressively than near-vertical ones. What's left when the etch finishes is a spacer: a thin insulating collar hugging each side of the gate, with no separate alignment step required at all.

The spacer then directly determines where the source and drain implants land, tying this back to the ion implantation step covered earlier. With the spacer in place along the gate's sidewalls, the subsequent ion implantation step is blocked by the spacer immediately adjacent to the gate, so dopant ions only reach silicon starting a controlled, spacer-width distance away from the gate edge. This is precisely the self-aligned source/drain formation that gives transistors consistent, repeatable electrical behavior across billions of instances on a chip — the spacer's width, set by how thick the original conformal deposit was, becomes one of the most carefully tuned dimensions in the entire transistor design, directly trading off switching speed against leakage control.

Spacers are a clear example of how this entire fab process chain is really one interconnected system rather than a list of independent steps. The spacer step alone touches lithography's earlier gate patterning, CVD's conformality requirements, plasma etch's directional control, and ion implantation's placement — all working together to solve one specific, small-scale positioning problem that has an outsized effect on final transistor performance. For AI accelerator manufacturing, where billions of transistors must all behave near-identically for a chip to function reliably, this kind of self-aligned, deposit-then-etch-back structure is exactly the sort of quiet engineering detail that makes consistent, high-yield production of extremely dense, extremely uniform transistor arrays possible at all.