IR Drop
IR drop is the reduction in voltage that occurs as current flows through the resistance of a chip's power distribution network, meaning circuits located farther from the power source can actually receive a noticeably lower voltage than the supply is providing.
IR drop exists because the metal wiring that distributes power across a chip, however well designed, still has real electrical resistance, and any current flowing through a resistance necessarily produces a voltage drop proportional to that current and resistance, exactly as basic circuit theory predicts. Since a chip's power distribution network must carry current from a limited number of power source connections out to circuits spread across the entire chip area, and every segment of wiring along that path adds a small amount of resistance, the cumulative voltage drop, current multiplied by resistance, can become significant for circuits located far from the power source or drawing especially heavy current.
| Aspect | Circuit near power source | Circuit far from power source |
|---|---|---|
| Resistance in the current path | Lower | Higher |
| Voltage actually received | Close to target | Reduced by IR drop |
| Risk of timing or logic issues | Lower | Higher if drop is excessive |
| Common use | Fine even with a leaner power grid | Needs robust grid design to stay safe |
Excessive IR drop can meaningfully affect a chip's behavior, since circuits operating at a lower-than-intended voltage tend to switch more slowly, and severe enough voltage reduction can even cause outright functional errors in sensitive circuitry. Because a circuit's switching speed generally depends on the voltage actually powering it, not just the voltage the source is nominally supplying, significant IR drop can introduce timing problems that weren't accounted for in analysis based on the ideal supply voltage, making IR drop a serious concern for both performance and correctness.
Chip designers combat IR drop primarily by building a robust power distribution network with wide, low-resistance metal wiring and numerous connection points spread across the chip, reducing both the resistance current must travel through and the distance it must travel. Because a denser grid of wider power wiring, with more connection points feeding current in from multiple locations rather than just a few, reduces both the effective resistance and the distance to any given circuit, careful power grid design is one of the primary tools chip designers use to keep IR drop within acceptable limits across the whole chip.
IR drop analysis has become an increasingly important step in the chip design flow as transistor density and switching activity have both increased, since more circuits switching simultaneously draw more instantaneous current through the same resistive power grid. Because packing more transistors into the same area while also running them at higher activity levels increases the total current the power grid must carry, and higher current directly worsens IR drop through that same resistance, modern chip design flows dedicate significant analysis effort specifically to verifying that IR drop stays within acceptable bounds everywhere on the chip.
Read IR drop through a garden-hose lens: much like water pressure at the far end of a long garden hose is noticeably weaker than pressure right at the spigot due to friction along the hose, voltage at a circuit far from the power source is noticeably weaker than the supply voltage due to resistance along the power distribution network.