What Is Known Good Die
A known good die, or KGD, is a die that has been electrically tested and verified to meet its full performance and quality specifications before being assembled into a package — a step that matters enormously once a die is going into a multi-die or chiplet-based assembly, where one untested bad die can ruin an otherwise expensive, fully assembled package.
KGD testing matters most in multi-die and chiplet-based packaging, where combining several dies into one assembly means a single bad die can ruin the whole expensive package. In a simple single-die package, a defective die is usually caught and discarded relatively cheaply; but once multiple dies are combined into one multi-die or chiplet-based assembly, an unverified bad die included in that assembly can cause the entire, far more expensive finished package to fail — this asymmetric cost is exactly why confirming each die is a known good die before assembly has become such a critical step.
| Aspect | Untested die | Known good die |
|---|---|---|
| Verification | Not yet electrically tested | Tested and confirmed to meet full spec |
| Risk in multi-die packaging | High — a bad die can ruin the assembly | Low — pre-verified before assembly |
| Common use | Simple single-die packages | Chiplets, multi-die and 3D packages |
| Testing approach | N/A | Wafer-level probe, temporary-carrier burn-in |
KGD testing has grown considerably more important as chiplet-based and multi-die packaging have become more common, since the cost of a single bad die failing scales with the value of the entire finished assembly. As chip designs have increasingly moved toward combining multiple smaller dies or chiplets into one package rather than relying on a single large monolithic die, ensuring each individual die is a known good die before it enters that expensive assembly process has become a much higher priority than it was for simpler, single-die packaging.
Achieving genuine KGD confidence is harder than testing a fully packaged chip, because die-level test access and thermal behavior differ meaningfully from a finished, packaged part. Testing a bare die on a wafer or a temporary carrier doesn't always perfectly replicate the electrical and thermal conditions of a fully packaged, assembled chip, which is why correlating die-level KGD test results to how a die will actually behave once packaged remains an active area of test engineering attention.
KGD test methodologies commonly include wafer-level electrical testing before dicing, sometimes supplemented by temporary-carrier burn-in testing after dicing but before permanent packaging. Depending on how much test confidence a given multi-die assembly requires, chipmakers may rely on wafer-level probe testing alone, or add an additional burn-in step using a temporary carrier to stress-test the individual die further before committing it to a permanent, harder-to-rework package.
Read known good die through a pre-qualified-parts lens: rather than discovering a defective die only after it has already been built into an expensive multi-die package, KGD testing confirms each die's quality beforehand — much like verifying every individual component before assembling them into a single, harder-to-repair finished product.