What Is Metrology
Metrology and inspection are how a fab knows whether the last 60 process steps actually worked, without waiting until the finished chip fails to find out. After nearly every lithography, etch, deposition, implant, or CMP step, wafers get pulled aside and checked before moving on. Metrology answers "how much" — how wide is this feature, how thick is this film, how well aligned is this layer to the one below it. Inspection answers a different question — "is something here that shouldn't be" — a stray particle, a void, a pattern bridge, a scratch. Together they're the quality-control loop threaded through the entire fab flow, not a single step at the end.
The tricky part is that most of this checking has to happen without damaging or destroying the wafer, because it's still mid-process. A handful of measurement techniques make this possible without slowing the line to a crawl: critical-dimension SEM (CD-SEM) images feature widths with an electron beam; overlay metrology measures how precisely one patterned layer lines up with the layer beneath it; scatterometry (also called Optical Critical Dimension, OCD) bounces light off a periodic test pattern and reconstructs its shape from how the light scatters, all without physically touching or damaging anything. Defect inspection tools scan the whole wafer or fast-sample it, comparing what they see against a reference die to flag anything unexpected.
Every measurement site feeds a statistical process control (SPC) chart, not just a pass/fail stamp on one wafer. Instead of trusting a single reading, fabs sample multiple sites across a wafer and multiple wafers across a lot, tracking the results against upper and lower control limits over time. A single out-of-spec reading might be noise; several trending in the same direction is the earliest possible warning that a tool is drifting out of calibration — and catching that drift here, mid-process, is far cheaper than discovering it only after a finished chip fails electrical test.
| Technique | What It Measures | Damages Wafer? | Speed |
|---|---|---|---|
| CD-SEM | Feature width / critical dimension | No (electron beam, non-contact) | Slower, high precision |
| Overlay metrology | Layer-to-layer alignment accuracy | No (optical, on test targets) | Fast |
| Scatterometry (OCD) | 3D profile shape from light scattering | No (optical, non-contact) | Very fast |
| Optical/E-beam defect inspection | Particles, voids, pattern defects | No (scan/sample only) | Optical: fast; E-beam: slower, higher resolution |
At advanced nodes, the tolerance for error at this checkpoint keeps shrinking even as the number of layers to check keeps growing. Overlay budgets between metal layers are now measured in single-digit nanometers, and a chip with 60-plus patterned layers has that many opportunities for a small alignment or dimension error to compound into a device that doesn't work — or one that works but degrades early in the field. Metrology and inspection are what let a fab catch that error at layer 12 instead of finding it in a customer's returned part, which is exactly why these checkpoints run continuously through the entire flow rather than once at the end.