What Is Wafer Test
Once the last metal layer is done, a finished wafer is still just a fragile glass-thin disc holding hundreds of identical, untested chips. Everything up to this point — lithography, etch, deposition, doping, CMP, interconnect — happens across the whole wafer at once. Wafer test, dicing, and packaging are the three steps that turn that shared disc into individual, verified, physically protected chips a customer can actually solder onto a board.
Wafer probe test happens before the wafer is ever cut, and it decides which die are even worth packaging. A probe card — a dense array of tiny spring-loaded needles — lands on each die's bond pads while it's still attached to the wafer, running electrical go/no-go tests and sometimes measuring how fast that specific die can run (speed binning, the same reason two chips with the same model number can ship at different clock speeds). The result is a wafer map: a grid marking every die as good or bad. That map is what saves money — a die that fails probe test never gets carried through dicing and expensive packaging, since there'd be nothing to save.
Dicing has to cut through solid silicon without cracking the circuits sitting right next to the cut line. Between every die on the wafer sits a scribe line — a narrow strip with no active circuitry, left there specifically so a precision saw or laser can cut through it without touching a working transistor. Even a hairline crack that strays into a die's active area can kill a chip that passed probe test moments earlier, which is why dicing tolerances are tight and the process is monitored almost as closely as the fab steps before it.
| Packaging Type | Structure | Typical Use | Key Advantage |
|---|---|---|---|
| Wire bond | Die wired to package with thin gold/copper wires | Simple, low-cost chips | Cheap, mature, low complexity |
| Flip chip | Die flipped, solder bumps connect directly to substrate | Higher pin-count, higher performance chips | Shorter, lower-inductance connections |
| 2.5D (CoWoS) | Multiple die placed on a shared silicon interposer | AI accelerators pairing compute die with HBM | Combines separately-made die into one package |
| 3D stacking (HBM/TSV) | Dies stacked vertically, connected through silicon | High-bandwidth memory stacks | Massive bandwidth in a small footprint |
This is exactly where the "why layer count matters" story from earlier comes full circle. A single monolithic die can only get so large before it hits the reticle limit (the biggest area a lithography scanner can expose in one shot) and before yield drops sharply with size — more area means more chances for a single defect to kill the whole die. Advanced packaging is the industry's answer: instead of building one enormous chip, combine several smaller, individually tested known-good die — compute tiles plus HBM memory stacks — into one package via CoWoS interposers and TSV-based 3D stacking. The AI accelerators built today aren't single chips at all; they're carefully tested, carefully packaged systems of chips, and wafer test is what makes sure only the good ones ever make it into that package in the first place.