Yield Modeling

Yield — Good Dies per Wafer Y = e^(-D0 · A) — defect density times die area determines how many chips survive fabrication Wafer Map (300mm) good die defective edge (partial) ~85% yield shown (typical mature node) Yield Models Poisson: Y = e^(-D0 · A) D0 = defect density (defects/cm²) A = die area (cm²) larger die → exponentially lower yield Murphy/Neg-Binomial: Y = (1 + D0·A/α)^(-α) more realistic — accounts for defect clustering Die Area vs Yield (D0 = 0.1 def/cm²) 50 mm² (small SoC): Y ≈ 95% 200 mm² (midsize): Y ≈ 82% 400 mm² (GPU): Y ≈ 67% 800 mm² (H100): Y ≈ 45% → this is why chiplets win: 4×200mm² > 1×800mm² yield Yield Ramp Lifecycle Early: 20-40% (learning, bring-up) Ramp: 50-70% (improving) Mature: 85-95% (production) N3 took 12+ months to reach 80% yield — each new node starts the learning curve over Economics: H100 die at 45% yield on $15K wafer → ~$2000 per good die (before packaging/test) Yield is the #1 factor in chip cost — 1% yield improvement at TSMC = billions in revenue Yield is the tax physics charges on ambition — bigger dies, newer nodes, tighter tolerances all reduce it.

Yield is the fraction of manufactured units that work — most commonly die yield, the share of dies on a wafer that pass test. It is the number that turns a process into a business: with hundreds of process steps where a single defect can kill a die, yield sets cost-per-good-die and gates whether a design is manufacturable at all.

A wafer holds many dies; a defect anywhere in a die usually kills it. Random particle and pattern defects land across the wafer at some average density D0 (defects per unit area). The larger a die, the more likely it catches at least one defect — so good dies cluster where defects happen to miss, and yield is simply good dies over total dies. Edge dies that fall off the round wafer are lost too, which is a second, geometric yield term separate from defects.

Yield falls exponentially with die area — this is the whole argument for chiplets. Under the simplest Poisson model, yield Y = e^(-A·D0): double the area A and yield drops sharply. Real defects cluster rather than scatter uniformly, so fabs use the Murphy or negative-binomial models, which are more forgiving than Poisson but keep the same shape. Either way, one big monolithic die yields far worse than several small ones doing the same work — so splitting a design into chiplets recovers yield and is often the difference between viable and not.

TermMeaningWhy it matters
Die yieldgood dies / total diesdrives cost-per-good-die
D0defect density (defects/cm2)lower = more good dies
Critical areaarea where a defect is fatallinks layout to yield
Poisson Y=e^(-A·D0)uniform-defect modelquick estimate
Murphy / neg-binomialclustered-defect modelsfab-accurate
Yield — the fraction of good dies, and why big dies are punished by defects green = good die · red = die hit by a defect · orange = defect good 45 / 52 on this wafer → die yield = 87% Yield vs die area (fixed defect density D₀) 25%50%75%100% Poisson Y=e^(-A·D₀) Murphy (clustered) die area → (bigger chip) Double the die area and yield falls exponentially — the core tension behind chiplets.

Yield is learned, not given. A new node starts at low yield and climbs a learning curve as engineers find and kill systematic defect sources; an excursion (a sudden tool or material problem) can crash it overnight. Fabs push yield up with defect-density reduction, design-for-manufacturing rules that shrink critical area, and redundancy plus repair (spare rows in memory, spare cores) so a defective unit can be salvaged rather than scrapped.

Read yield through a quant lens rather than a pass/fail lens: it is a probability that compounds over area and steps, and it flows straight into cost-per-good-transistor. Because Y = e^(-A·D0), the leverage is either lowering D0 or shrinking the die — which is exactly why chiplets, redundancy, and defect-density programs exist. Treat yield as a measured exponential to be engineered, not a fixed property of the process.

Take yield modeling further

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