AI Chip Process

# AI Chip Process: Sub-2nm Gate-All-Around (GAA), Atomic Layer Processing, and Manufacturing Physics

An AI chip process is the physical and chemical sequence that turns raw monocrystalline silicon into a high-density, multi-billion-transistor accelerator. At the sub-2nm node regime, classical planar CMOS and FinFET architectures reach their electrostatic breakdown limits: gate length shrinkage causes source-to-drain quantum tunneling, severe drain-induced barrier lowering (DIBL), and uncontrollable subthreshold leakage.

To overcome these quantum limits and sustain the exponential compute density demanded by transformer models, foundries transitioned to Gate-All-Around (GAA) nanosheets paired with atomic-scale processing (Atomic Layer Deposition, Atomic Layer Etching, Extreme Ultraviolet Photolithography) and Backside Power Delivery Networks (BSPDN).

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### The Anatomy of a Sub-2nm GAAFET Transistor

Inside a Sub-2nm Gate-All-Around (GAA) Transistor atomic cross-section: nanosheet ribbons, high-k metal gate, and dual-sided interconnects Frontside Signal Wire (M1 Copper) Source Si:P / SiGe Drain Si:P / SiGe Metal Gate (TiN / W) Si Nanosheet 1 (30nm × 5nm) Si Nanosheet 2 (30nm × 5nm) Si Nanosheet 3 (30nm × 5nm) Bottom Dielectric Isolation (BDI - SiO₂) Ru BPR Nano-TSV → Backside VDD Power Mesh (Thick Cu Rail) High-k ALD Gate Dielectric HfO₂/ZrO₂, 360° wrap Atomic Nanosheet Channel Tinv<0.7nm · Ion>1.2mA/µm Buried Power Rail Ru, >950°C stable Gate-all-around wraps electrostatic control on all 4 sides of the channel — cutting subthreshold leakage below 100 pA/µm Decoupled Backside Power (BSPDN) routes supply current directly into source/drain without congesting frontside signal metal

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### The Fundamental Physics: Quantum Electrostatics and Atomic Processing

#### 1. Gate-All-Around Electrostatic Scaling
In classical MOSFETs and FinFETs, the gate controls the channel across one, two, or three surfaces. As the physical channel length $L_g$ scales below $12\text{ nm}$, electrostatic field lines from the drain penetrate into the channel, causing severe Drain-Induced Barrier Lowering (DIBL) and gate control degradation.

The natural length $\lambda_g$ represents the spatial extent over which drain potential encroaches into the channel:

$$ \lambda_g = \sqrt{\frac{\epsilon_{ch}}{2 \epsilon_{ox}} t_{ch} \cdot t_{ox}} $$

Where $\epsilon_{ch}$ and $\epsilon_{ox}$ are channel and dielectric permittivities, $t_{ch}$ is nanosheet channel thickness ($t_{ch} \approx 5\text{ nm}$), and $t_{ox}$ is equivalent oxide thickness ($EOT \approx 0.65\text{ nm}$). To prevent punch-through and keep subthreshold swing near the theoretical thermodynamic limit ($SS \approx 60\text{ mV/decade}$ at $300\text{ K}$), the physical gate length must satisfy:

$$ L_g \ge 3 \cdot \lambda_g $$

By fully surrounding the silicon nanosheet channels on all four sides with high-$\kappa$ gate dielectric ($HfO_2$) and work-function metals, GAAFETs minimize $\lambda_g$, allowing channel lengths to safely scale down to $10\text{ nm}$ to $12\text{ nm}$ with near-zero leakage.

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### Atomic Layer Etching & Selective Nanosheet Release

Atomic-Scale Channel Release: SiGe Selective Etching isotropic dry etching removes sacrificial SiGe without attacking atomic silicon ribbons 1. Epitaxial Superlattice Silicon Substrate Si₀.₇Ge₀.₃ (Sacrificial) Si Sheet 1 (Channel) Si₀.₇Ge₀.₃ (Sacrificial) Si Sheet 2 (Channel) Si₀.₇Ge₀.₃ (Sacrificial) Si Sheet 3 (Channel) Gas ALE 2. Selective SiGe Etch Silicon Substrate Si Sheet 1 (Intact) Si Sheet 2 (Intact) Si Sheet 3 (Intact) 150:1 Select 3. Suspended Ribbons Silicon Substrate Open 10nm Gap Open 10nm Gap Open 10nm Gap Suspended Si Ribbons Atomic Layer Etching achieves >150:1 selectivity: sacrificial SiGe layers are completely cleared without thinning the 5nm silicon channels This prepares the open vertical gaps for 360-degree conformal Atomic Layer Deposition (ALD) of HfO₂ gate oxide.

#### 2. Atomic Layer Deposition (ALD) & Self-Limiting Surface Saturation
Once the sacrificial $Si_{0.7}Ge_{0.3}$ layers are cleared, the open $10\text{ nm}$ vertical gaps between suspended nanosheets must be lined with ultra-thin, pinhole-free dielectric and work-function metal layers. Standard Chemical Vapor Deposition (CVD) cannot coat high-aspect-ratio shadow regions uniformly.

Foundries deploy Atomic Layer Deposition (ALD), a sequential, self-limiting chemical reaction:
1. Pulse A: Precursor gas (e.g., hafnium tetrachloride $HfCl_4$ or TEMAH) is pulsed into the reactor, saturating surface hydroxyl groups ($-OH$) until steric hindrance halts adsorption at exactly one monolayer.
2. Purge A: High-purity nitrogen ($N_2$) or argon purges excess precursor molecules from the chamber.
3. Pulse B: Co-reactant gas (water vapor $H_2O$ or ozone $O_3$) is introduced, reacting with the adsorbed hafnium complex to form a uniform $HfO_2$ monolayer while releasing $HCl$ byproducts.
4. Purge B: Chamber is evacuated.

The cycle repeats $N$ times, with film thickness $t_{film}$ governed strictly by:

$$ t_{film} = N \cdot \text{GPC} $$

Where $\text{GPC}$ is Growth-Per-Cycle (typically $0.08 - 0.12\text{ nm/cycle}$). ALD delivers $100\%$ step coverage across all four faces of the suspended nanosheet channel, maintaining sub-angstrom dielectric thickness uniformity across a $300\text{ mm}$ wafer.

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### Process Evolution: FinFET vs. GAAFET vs. Complementary FET (CFET)

Process Metric5nm / 3nm FinFET (N5/N3)2nm GAAFET Nanosheet (N2/A16)Sub-1nm CFET (3D Stacking)
Channel OrientationVertical 3D FinHorizontal NanosheetsMonolithic 3D Stacked n-over-p
Effective Gate Control3-Sided Gate4-Sided Gate-All-Around (360°)4-Sided Gate-All-Around
Effective Channel Width ($W_{eff}$)$2 H_{fin} + W_{fin} \approx 110\text{ nm}$$2 N (W_{ns} + T_{ns}) \approx 210\text{ nm}$$2 N (W_{ns} + T_{ns})$ in half footprint
Drive Current ($I_{on}$ at $V_{DD}=0.7\text{V}$)$\sim 0.85\text{ mA/µm}$$\sim 1.25\text{ mA/µm}$ ($+45\%$)$\sim 1.30\text{ mA/µm}$
Subthreshold Swing ($SS$)$68 - 74\text{ mV/dec}$$62 - 65\text{ mV/dec}$ (near ideal)$62 - 64\text{ mV/dec}$
DIBL (Drain-Induced Barrier Lowering)$45 - 65\text{ mV/V}$$<25\text{ mV/V}$$<20\text{ mV/V}$
Power RoutingFrontside BEOL M0–M15Backside Power (BSPDN / BPR)Backside Power + 3D Interconnect
Standard Cell Area ShrinkBaseline$15\% - 20\%$ reduction$40\% - 50\%$ reduction

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### The Capital Compounding Flywheel and the Sub-2nm Process Moat

In semiconductor manufacturing, process leadership compounds through what Charlie Munger described as the cumulative volume learning curve:

$$ C_N = C_1 \cdot N^{-b} $$

Where $C_N$ is the defect cost of the $N$-th wafer, $C_1$ is initial prototype cost, and $b$ is the learning index ($b \approx 0.3 - 0.5$).
* A foundry that processes 100,000 sub-2nm GAAFET wafers per month discovers and eliminates atomic-scale defect modes (such as nanosheet stiction, inner spacer dishing, and Ru BPR voiding) four times faster than a competitor processing 10,000 wafers.
* High yield ($>85\%$) lowers die manufacturing costs, attracting marquee fabless AI designers (Apple, NVIDIA, AMD, Qualcomm).
* High cash generation funds the next generation of €380M High-NA EUV scanners and atomic layer cluster tools, widening the competitive barrier into an insurmountable capital toll bridge.

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