GAA/FinFET Transistor I-V & Short-Channel Simulator

Set a device geometry (gate length, body thickness, gate oxide EOT, gate architecture) and a bias point, then run it — the simulation executes on the ChipFoundryServices distributed compute pool. It computes the electrostatic screening length λ that decides how tightly the gate controls the channel, the short-channel penalties that follow (subthreshold swing, DIBL, threshold roll-off), and a velocity-saturated charge-transport model for the full Id-Vgs transfer and Id-Vds output curves — then reports Ion/Ioff, transconductance, the CV/I intrinsic delay and a switch-quality verdict. The transistor is the switch under every AI accelerator. Reduced-order educational model. See also the thermal, interconnect RC, CMP planarization, plasma-etch and lithography simulators and the compute-pool status.

N5 FinFET N2 GAA nanosheet Legacy planar
Transfer curve Id-Vgs (log) — slope is the subthreshold swing; span is Ion/Ioff
Output family Id-Vds — triode → saturation at four gate biases
Developer API — same simulation over HTTP (load-balanced across the pool): 
curl -X POST https://www.chipfoundryservices.com/edge/transistor \
  -H "Content-Type: application/json" \
  -d '{"gate_length_nm":16,"body_thickness_nm":6,"eot_nm":1.0,"gate_config":4,
       "vdd_v":0.75,"vgs_v":0.75,"vt0_v":0.30,"mobility_cm2_vs":300,"temperature_c":25}'
Returns JSON with outputs (natural_length_nm, ideality_n, subthreshold_swing_mv_dec, dibl_mv_v, vt_long_v, vt_eff_v, overdrive_v, ion_ua_um, ioff_na_um, ion_ioff_ratio, transconductance_us_um, gate_cap_ff_um2, intrinsic_delay_ps, carrier_mobility_cm2_vs, verdict), the full profile (121-point transfer curve, four-bias output family, geometry), the serving node, and compute_ms.