Chip Cost
Chip cost and fab economics define the massive capital investments and complex cost structures that determine semiconductor pricing — where a leading-edge fab costs $20 billion+ to build, a single wafer costs $10,000-$20,000 to process, and a mask set can exceed $15 million, making semiconductors one of the most capital-intensive industries in the world.
What Determines Chip Cost?
- Definition: The total cost per chip is determined by fab construction, wafer processing, mask costs, packaging, testing, and yield — divided across the number of good dies produced.
- Key Formula: Cost per die ≈ (Wafer cost / Good dies per wafer) + Packaging cost + Test cost.
- Scale Dependency: High-volume products (billions of units) achieve extremely low per-unit costs; low-volume ASICs can cost $50-$500+ per chip.
Why Fab Economics Matter
- Barrier to Entry: Only 3 companies (TSMC, Samsung, Intel) can manufacture at leading-edge nodes — the $20B+ fab cost eliminates most competitors.
- Pricing Pressure: Chip customers demand lower prices every year, requiring fabs to continuously improve yield and throughput to maintain margins.
- Design Choices: The cost of masks and process development forces companies to choose between cutting-edge performance (expensive) and mature nodes (cost-effective).
- Geopolitics: Governments invest $50-100B+ (CHIPS Act, EU Chips Act) because domestic semiconductor manufacturing is strategic infrastructure.
Fab Construction Costs
| Fab Type | Approximate Cost | Process Node | Example |
|---|---|---|---|
| Leading-edge logic | $20-28B | 3-5nm | TSMC Arizona |
| Advanced logic | $10-15B | 7-14nm | Samsung Taylor |
| Mature node | $3-8B | 28-65nm | GlobalFoundries |
| Specialty (analog/power) | $1-5B | 90-180nm | Infineon, TI |
| DRAM | $10-15B | 1α-1β nm | SK hynix, Micron |
| 3D NAND | $10-20B | 200+ layers | Samsung, Kioxia |
Wafer Processing Costs
- Leading-Edge (3-5nm): $16,000-$20,000 per 300mm wafer — includes 80+ lithography layers, some with EUV ($150M per scanner).
- Mainstream (14-28nm): $3,000-$8,000 per wafer — DUV lithography with multi-patterning.
- Mature (65-180nm): $1,000-$3,000 per wafer — simpler processes, fully depreciated equipment.
- Processing Steps: Leading-edge chips require 1,000+ individual process steps over 2-3 months of fabrication.
Mask Set Costs
- 5nm Node: $15-20 million per mask set (80+ masks, many EUV).
- 7nm Node: $10-15 million (DUV multi-patterning).
- 28nm Node: $1-3 million.
- 180nm Node: $200K-$500K.
- Impact: Mask cost amortized over production volume — 1 million chips amortizes a $15M mask set to $15/chip; 1,000 chips would be $15,000/chip.
Cost Per Die Example
| Component | Leading-Edge (5nm) | Mainstream (28nm) |
|---|---|---|
| Wafer cost | $17,000 | $4,000 | |
| Dies per wafer | 400 | 800 |
| Wafer yield | 80% | 95% |
| Good dies | 320 | 760 |
| Die cost | $53.13 | $5.26 | |
| Packaging | $5-50 | $1-5 | |
| Testing | $1-5 | $0.50-2 | |
| Total per chip | $59-108** | **$6.76-12.26 |
Industry Economics
- Capital Intensity: Semiconductor fabs have the highest capital expenditure per revenue dollar of any manufacturing industry.
- Depreciation: Fab equipment depreciates over 5-7 years — mature fabs with fully depreciated equipment have much lower operating costs.
- Utilization: Fabs must run at 80-95% utilization to be profitable — even brief periods of low demand can cause significant losses.
- R&D Cost: Developing a new process node costs $3-5 billion in R&D over 3-5 years before first revenue.
Chip cost and fab economics are the driving force behind the entire semiconductor industry structure — dictating which companies can compete at leading edge, why foundry models dominate, and why governments invest hundreds of billions to secure domestic chip manufacturing capacity.