Custom Cell Layout
Custom Analog Cell Layout is the manual, transistor-level physical design of circuits where precise geometric control of device placement, matching, symmetry, and parasitic management is essential for circuit performance — required for analog blocks (amplifiers, data converters, PLLs, voltage references, bandgaps) where automated place-and-route cannot achieve the device matching, noise isolation, and parasitic control that analog functionality demands, making custom layout one of the most specialized and skill-intensive disciplines in IC design.
Why Custom Layout for Analog
- Digital cells: Automated P&R handles millions of standard cells → acceptable variation.
- Analog circuits: Performance depends on precise transistor matching (< 0.1% mismatch).
- Automated tools cannot guarantee:
- Symmetric current paths for differential pairs.
- Common-centroid device placement for matched pairs.
- Minimal parasitic capacitance on sensitive nodes.
- Proper guard rings and shielding for noise isolation.
Matching Techniques
| Technique | Purpose | How |
|---|---|---|
| Common centroid | Cancel linear gradients | Interdigitate A-B-B-A pattern |
| Interdigitation | Average out process variation | Alternate finger placement |
| Dummy devices | Uniform etch environment | Extra devices at array edges |
| Symmetric routing | Equal parasitics on matched paths | Mirror route topology |
| Same orientation | Cancel crystal direction effects | All matched devices same rotation |
| Unit cell | Quantize to identical elements | Same width/length for all units |
Common Centroid Layout (Differential Pair)
Current Mirror Layout
- Reference and mirror transistors: Same W/L, same orientation.
- Minimize distance between devices → reduce mismatch.
- Share source/drain connections → reduce parasitic resistance mismatch.
- Gate routing: Equal length, symmetric → same gate resistance.
Parasitic-Sensitive Layout Rules
| Rule | Purpose |
|---|---|
| Minimize drain area on cascode nodes | Reduce parasitic capacitance → preserve bandwidth |
| Short gate connections | Reduce distributed RC → lower noise |
| Wide metal on current paths | Reduce IR drop → improve matching |
| Ground shield under sensitive routes | Block substrate coupling |
| Avoid routing over resistors | Prevent coupled noise |
FinFET / GAA Custom Layout Challenges
- Fin quantization: Device width = N × fin pitch. No arbitrary sizing.
- Contact-over-active-gate (COAG): Enables smaller area but constrains routing.
- Middle-of-line (MOL): Limited routing options near devices → constrains analog interconnect.
- Regularity requirements: Design rules push toward gridded, regular layouts → limits analog flexibility.
Layout Verification for Analog
- LVS: Must exactly match schematic including parasitic devices, guard rings.
- Post-layout extraction (PEX): Extract all parasitic R, C, L → simulate to verify performance.
- Parasitics budget: Compare pre-layout (schematic) vs. post-layout performance → iterate if degraded.
- Monte Carlo with parasitics: Statistical simulation with extracted parasitics → verify yield.
Custom analog layout is the craft that turns analog circuit theory into working silicon — while digital design automation has replaced most manual layout work, analog circuits remain stubbornly resistant to automation because the performance of every amplifier, data converter, and reference circuit depends on layout details that only an experienced analog layout engineer can optimize, making this skill one of the scarcest and most valued in the semiconductor industry.