Ferroelectric FET
Ferroelectric FET (FeFET) is a non-volatile memory transistor that uses a ferroelectric material in the gate stack to store data as polarization states — combining logic and memory in a single device with near-zero standby power, nanosecond switching, and CMOS-compatible integration using doped HfO2.
How FeFET Works
- Ferroelectric Gate: The gate dielectric contains a thin ferroelectric layer (typically doped HfO2).
- Polarization States: Applying a voltage pulse switches the ferroelectric polarization direction (up or down).
- Threshold Voltage Shift: Different polarization states shift the transistor's Vt — creating two distinct logic states.
- Polarization UP → Low Vt → High read current → Logic "1".
- Polarization DOWN → High Vt → Low read current → Logic "0".
- Non-Volatile: Polarization is retained without power — data persists.
Why HfO2 Ferroelectrics Changed Everything
- Traditional ferroelectrics (PZT, SBT) were CMOS-incompatible — contained Pb, required thick films.
- Discovery (2011): Doped HfO2 (Si-doped, Zr-doped) is ferroelectric at 5–10 nm thickness.
- HfO2 is already used in HKMG process — minimal integration disruption.
- Scalable to advanced nodes (sub-10 nm films).
FeFET vs. Other Non-Volatile Memories
| Metric | Flash (NAND) | RRAM | STT-MRAM | FeFET |
|---|---|---|---|---|
| Write Speed | ~100 μs | ~10 ns | ~10 ns | ~10 ns |
| Write Energy | High | Medium | Medium | Low |
| Endurance | 10⁵ cycles | 10⁶–10⁹ | > 10¹² | 10⁴–10⁸ |
| Cell Size | 4F² (3D) | 4F² | 6-30F² | ~1T (smallest) |
| CMOS Compatibility | Separate | Good | Good | Excellent |
Applications
- Embedded Non-Volatile Memory: Replace eFlash in MCUs — faster, smaller, lower power.
- Compute-in-Memory: FeFET arrays perform multiply-accumulate operations — analog AI acceleration.
- Neuromorphic Computing: Analog weight storage with multi-level polarization.
FeFET is a leading candidate for next-generation embedded non-volatile memory — the discovery that HfO2 is ferroelectric at nanoscale thickness unlocked a path to memory-logic integration that is fully compatible with existing CMOS manufacturing.