FinFET to Nanosheet Evolution
Gate-All-Around (GAA) nanosheet field-effect transistors, Multi-Bridge Channel FETs (MBCFET), and vertically stacked ribbon architectures constitute the advanced three-dimensional CMOS device technologies engineered to overcome the physical scaling limits of FinFETs below the 3nm node. In modern nanoscale logic fabrication, as transistor gate lengths shrink below fifteen nanometers and fin pitches contract, the three-sided gate architecture of traditional FinFETs experiences severe electrostatic gate control degradation, resulting in intolerable subthreshold leakage currents, drain-induced barrier lowering (DIBL), and discrete quantized drive currents. Gate-All-Around nanosheets resolve these fundamental short-channel bottlenecks by wrapping the high-k metal gate dielectric stack completely around all four surfaces of multiple vertically stacked horizontal silicon channels. Fabricating GAA nanosheet transistors requires precise epitaxial growth of alternating silicon and silicon-germanium ($\text{Si/SiGe}$) superlattice layers, selective lateral chemical etching to form inner dielectric spacers, isotropic sacrificial $\text{SiGe}$ channel release, and conformal atomic layer deposition (ALD) replacement metal gate encapsulation.
The architectural benefit is stronger electrostatic leverage at a given channel geometry, not a universal node-independent performance number. FinFET drive is quantized mainly by fin count; nanosheets add width, thickness, spacing, and stack count as design and process variables. Those knobs also change gate capacitance, series resistance, release and fill difficulty, variability, self-heating, and standard-cell integration, so comparisons must hold the electrical and layout targets constant.
The Gate-All-Around nanosheet architecture provides complete four-sided electrostatic gate encirclement to suppress short-channel effects. In traditional planar MOSFETs and 3D FinFETs, the gate electrode controls the channel from one or three sides, allowing sub-surface leakage paths to conduct parasitic drain-to-source currents as channel lengths shrink. By fully enclosing each horizontal nanosheet channel with a high-k dielectric and metal gate stack, the gate electrode establishes symmetric electric fields across top, bottom, and sidewall surfaces. Strong gate coupling reduces the body-factor penalty and can move subthreshold swing ($\text{SS}$) toward—but not below for conventional thermionic MOS operation in equilibrium—the temperature-dependent thermal limit. Real swing also includes depletion or quantum capacitance, interface traps, short-channel electrostatics, bias, and measurement conditions:
Drain-Induced Barrier Lowering ($\text{DIBL} = \Delta V_{\text{th}} / \Delta V_{\text{DS}}$) can improve relative to a less controlled geometry. Achieved DIBL, supply voltage, leakage, and delay depend on gate length, sheet geometry, materials, contacts, process, circuit target, and bias.
Epitaxial superlattice growth and selective isotropic etching dictate nanosheet channel thickness and suspension geometry. Nanosheet fabrication begins by depositing an epitaxial superlattice composed of alternating monocrystalline silicon channels ($\text{Si}$, thickness $t_{\text{Si}} \approx 5\text{--}6\text{ nm}$) and sacrificial silicon-germanium spacer layers ($\text{Si}_{0.70}\text{Ge}_{0.30}$, thickness $t_{\text{SiGe}} \approx 8\text{--}10\text{ nm}$) using ultra-high-vacuum chemical vapor deposition (UHV-CVD). Following vertical fin etching and dummy poly-silicon gate patterning, a highly selective isotropic chemical vapor or wet etch (using vapor-phase $\text{HCl}$ or $\text{HF}/\text{H}_2\text{O}_2/\text{CH}_3\text{COOH}$ solutions) strips the sacrificial $\text{SiGe}$ layers with an etch selectivity exceeding $150:1$ relative to pure silicon. This releases vertically stacked silicon nanosheets for conformal interface-layer, dielectric, and work-function-metal deposition. Thickness, corner shape, residual sacrificial material, surface loss, strain relaxation, and vertical gaps must be measured; release does not guarantee pristine or identical channels.
| Transistor Architecture | Gate Control Geometry | Effective Conduction Width ($W_{\text{eff}}$) | Typical Subthreshold Swing ($\text{SS}$) | Typical DIBL | Channel Width Flexibility | Target Node Implementation |
|---|---|---|---|---|---|---|
| Planar Bulk MOSFET | 1-Sided Top Gate | $W_{\text{planar}}$ | $85\text{--}105\text{ mV/dec}$ | $> 100\text{ mV/V}$ | Continuous layout width | Mature legacy nodes ($> 28\text{nm}$) |
| Bulk 3D FinFET | 3-Sided (Top + 2 Sides) | $2 H_{\text{fin}} + W_{\text{fin}}$ | $70\text{--}78\text{ mV/dec}$ | $45\text{--}65\text{ mV/dec}$ | Discrete quantized fin count | $16\text{nm}\text{ to }3\text{nm}$ logic nodes |
| Multi-Bridge Nanosheet GAA | 4-Sided All-Around Wrap | $2(W_{\text{sheet}} + H_{\text{sheet}}) \times N$ | $64\text{--}66\text{ mV/dec}$ | $< 35\text{ mV/V}$ | Fully continuous ($15\text{--}60\text{nm}$) | $3\text{nm}, 2\text{nm}, \text{A16/A14}$ |
| Forksheet FET | 3-Sided with Dielectric Wall | Reduced footprint | $66\text{--}68\text{ mV/dec}$ | $< 40\text{ mV/V}$ | Continuous with tight N-to-P | $2\text{nm}\text{ and }1.4\text{nm}$ standard cells |
| Complementary FET (CFET) | Monolithic 3D Stacked GAA | 3D stacked NMOS over PMOS | $64\text{--}66\text{ mV/dec}$ | $< 35\text{ mV/V}$ | Maximum standard cell density | Sub-$1\text{nm}$ future scaling ($\text{A10/A7}$) |
Inner dielectric spacers isolate the all-around gate from source/drain epitaxy and control—not eliminate—parasitic capacitance. After fin patterning and prior to source/drain epitaxial regrowth, the exposed ends of the sacrificial $\text{SiGe}$ layers are laterally etched back by four to six nanometers. An atomic layer deposition (ALD) low-k dielectric film—such as silicon boron carbon nitride ($\text{SiBCN}$, $k \approx 4.0\text{--}4.5$) or silicon oxycarbonitride ($\text{SiOCN}$)—is conformally deposited and anisotropically etched back to form self-aligned inner spacers in the lateral $\text{SiGe}$ recesses. These inner spacers define the physical channel length, block gate metal encroachment into the source/drain junctions, and minimize parasitic gate-to-source/drain overlap capacitance ($C_{\text{ov}}$), preserving high switching speeds and preventing high-frequency RC performance roll-off.
Continuous channel width design freedom enables precise drive current customization and power optimization in standard cell layouts. Unlike FinFET architectures, where drive current is strictly quantized by integer numbers of discrete vertical fins ($1\text{-fin}, 2\text{-fin}, 3\text{-fin}$), GAA nanosheets permit continuous layout-level adjustment of the sheet width ($W_{\text{sheet}} = 15\text{ nm}\text{ to }60\text{ nm}$). A perimeter expression provides first-order intuition for intrinsic channel capability, but realized drive also depends on electrostatics, transport, contact and access resistance, capacitance, sheet nonuniformity, and self-heating:
where $H_{\text{sheet}}$ is sheet thickness ($5\text{ nm}$), $N_{\text{sheets}}$ is the number of stacked sheets ($3\text{ to }4$), $v_{\text{sat}}$ is carrier saturation velocity, and $Q_{\text{inv}}$ is inversion charge density. Circuit designers can deploy wide nanosheets ($W_{\text{sheet}} \ge 50\text{ nm}$) along critical clock and datapath execution paths to maximize drive current ($I_{\text{on}} > 1.5\text{ mA/}\mu\text{m}$), while utilizing narrow nanosheets ($W_{\text{sheet}} \le 20\text{ nm}$) in high-density SRAM bitcells to minimize active power consumption.
The stack converts process variation into correlated electrical variation. Sheet thickness and corner shape alter electrostatic control and transport; channel release and conformal gate fill can differ by vertical position; inner-spacer length changes both effective channel geometry and fringe capacitance; and source/drain plus contact resistance limits the current delivered outside the intrinsic channel. A useful GAA comparison therefore reports distributions of intrinsic and extrinsic metrics rather than inferring circuit performance from wrapped-gate geometry or total perimeter alone.
Delivering ultra-dense logic compute scaling and extreme energy efficiency across sub-2nm nodes requires evaluating transistor physics through a gate-all-around-nanosheet-mbcfet-and-electrostatic-scaling lens. By uniting $\text{Si/SiGe}$ epitaxial superlattice growth, selective vapor-phase channel release kinetics, low-k inner spacer engineering, four-sided atomic layer replacement metal gate encapsulation, and continuous nanosheet width optimization, transistor architecture teams sustain Moore's Law. Mastering Gate-All-Around fundamentals guarantees that high-performance AI accelerators, server microprocessors, and ultra-low-power mobile systems transition into sub-2nm and Angstrom-era fabrication with mathematically proven electrostatic integrity and maximum switching performance.