Floorplan Optimization
Floorplan Optimization is the strategic placement of hard macros (memories, PLLs, I/O pads), soft blocks (logic modules), and power/clock structures to minimize die area, wire length, congestion, and timing while meeting physical constraints — the first and most impactful physical design step where decisions made here propagate through every subsequent stage of the implementation flow.
Why Floorplanning Matters
- A good floorplan: 10-15% less area, 15-20% better timing, 10-20% less power.
- A bad floorplan: No amount of P&R optimization can recover — may require complete redo.
- Floorplanning is still heavily manual/semi-automated for complex SoCs — requires architectural understanding.
Floorplan Elements
| Element | Placement Rules | Impact |
|---|---|---|
| Die size/shape | Rectangular, aspect ratio ~1:1 to 1:1.5 | Determines package, cost |
| I/O pads / bumps | Around die periphery or area array | Signal routing quality |
| Hard macros (SRAM, ROM) | Fixed placement, orientation matters | Routing blockage, timing |
| Analog blocks | Edge/corner, away from digital noise | Signal integrity |
| PLL / Clock | Central or near distribution center | Clock skew |
| Power switches | Distributed within power-gated domain | IR drop, rush current |
Floorplan Constraints
- Macro spacing: Minimum gap between macros for routing channels (6-12 tracks).
- Macro orientation: SRAM orientation affects pin accessibility — wrong orientation blocks routing.
- Halo/keepout: Exclusion zones around macros where no cells placed.
- Blockages: Routing and placement blockages for sensitive analog areas.
- Pin placement: Chip I/O pin assignment matched to package ball map.
Optimization Objectives
1. Minimize wirelength: Place connected blocks close together → less wire → less delay, power.
2. Minimize congestion: Avoid routing hotspots — distribute routing demand evenly.
3. Timing closure: Critical paths have short physical distance → easier timing.
4. Power delivery: Power pads distributed for uniform IR drop.
5. Thermal: Spread high-power blocks to avoid hotspots.
Floorplan Exploration
- Manual: Experienced designers place blocks based on connectivity, timing, power.
- Automated: EDA tools (Innovus, ICC2) offer macro placement optimization.
- Simulated annealing, genetic algorithms explore macro arrangements.
- AI-assisted: Google DeepMind, NVIDIA, and EDA vendors exploring RL-based floorplanning.
Hierarchical Floorplanning
- Large SoCs (> 100M gates): Floorplanned hierarchically.
- Top-level: Place major subsystems (CPU cluster, GPU, memory controller).
- Block-level: Each subsystem floorplanned independently.
- Interface: Top-level tracks provide feedthrough routing between blocks.
Floorplan optimization is the architectural blueprint of physical chip design — it translates the logical design hierarchy into a physical arrangement that determines area efficiency, performance, and manufacturability, making it the single design step with the highest leverage on overall implementation quality.