Foundry

A foundry is the manufacturing layer of the semiconductor industry: it takes a customer's finished chip layout and turns it into working wafers through a controlled sequence of lithography, deposition, etch, implant, metrology, and yield-learning steps — without ever touching the chip's actual design.

The Foundry Ecosystem: Who Does What design and manufacturing split into separate companies — and a feedback loop ties them back together EDA & IP Synopsys · Cadence Arm · Siemens EDA Fabless Designer NVIDIA · AMD Qualcomm · startups Foundry TSMC · Samsung GlobalFoundries · UMC OSAT ASE · Amkor JCET tools & blocks GDSII layout bare die wafer yield data, DRC/LVS feedback, process-window limits Why the split exists A fab costs $10–20B+ to build at leading-edge nodes. Few companies can carry that capital load AND design chips. Splitting design from manufacturing let hundreds of fabless startups exist — but it also means foundry capacity access became one of the most strategically contested resources in modern technology.

The industry exists because design and manufacturing scaled apart. A fabless company can focus entirely on architecture, RTL, verification, software, and go-to-market, while a foundry absorbs the capital intensity of process technology and factory operations — a single leading-edge fab now costs $10–20 billion to build. That split made the modern chip startup possible. It also turned foundry capacity into one of the most strategically contested resources in technology: when demand outstrips capacity, access — not just price — becomes the constraint.

Who does what:

RoleOwnsExamples
EDA & IPTools, verification, reusable silicon blocksSynopsys, Cadence, Siemens EDA, Arm
Fabless designerThe chip's architecture and productNVIDIA, AMD, Qualcomm, most startups
FoundryManufacturing wafers from a customer's layoutTSMC, Samsung Foundry, GlobalFoundries, UMC
OSATPackaging and testing finished dieASE, Amkor, JCET

It's a loop, not a one-way handoff. The diagram above shows the forward flow — IP into design, design into manufacturing, bare die into packaging — but real engagements run a feedback path too: wafer yield data, DRC/LVS violations, and process-window limits flow back from the foundry to the fabless design team, shaping the next design revision before it ever reaches silicon. A foundry that only manufactures without that feedback loop produces chips; one that closes the loop improves them generation over generation — which is exactly what keeps Moore's Law-era scaling alive even as physics gets harder.

Take foundry further

Ask the copilot about this term, or have our engineers assess it against your process.