Gate Cut
Gate Cut and Single Diffusion Break (SDB) are the CMOS patterning techniques that use a separate cut mask to sever continuous gate or fin lines at precise locations, creating isolated transistors from what was originally patterned as uninterrupted features — enabling unidirectional patterning (simpler lithography with only one orientation of lines) while defining individual cells and circuit boundaries through post-patterning cuts rather than trying to print complex 2D shapes in a single lithography step.
Why Gate Cut / Fin Cut
- At sub-14nm: 2D shapes are extremely difficult to print → lithography works best for straight parallel lines.
- Unidirectional patterning: Print all gates as continuous parallel lines → simple 1D pattern.
- Then cut: Use second mask to cut lines where transistors must be isolated.
- Result: Each cell boundary defined by cut, not by complex 2D pattern.
Types of Cuts
| Cut Type | What Is Cut | Purpose |
|---|---|---|
| Gate cut (CPODE) | Poly/metal gate line | Separate adjacent gate electrodes |
| Fin cut (CFIN) | Silicon fin | Separate adjacent transistor channels |
| Metal cut | Interconnect metal line | Separate adjacent wires |
| Contact cut | Contact/via rail | Separate shared contacts |
CPODE: Cut Poly on Diffusion Edge
- CPODE placed between two cells along abutment boundary.
- Without CPODE: Need wider spacing between cells (double diffusion break) → area waste.
- With CPODE: Single cut → saves one gate pitch per boundary → 10-15% area reduction.
Single vs. Double Diffusion Break
| Feature | SDB (Single) | DDB (Double) |
|---|---|---|
| Gate pitches used | 1 | 2 |
| Area efficiency | Better | Worse |
| Isolation | Moderate | Better |
| Process complexity | Higher (needs cut mask) | Lower |
| Usage | Cell boundaries | Power domain boundaries |
Gate Cut Process
1. Pattern full gates as continuous lines (main litho + etch).
2. Deposit dummy gate material (replacement gate flow).
3. Apply cut mask (EUV or immersion + SADP) → expose cut regions.
4. Etch: Remove gate material in cut regions → leaves gap.
5. Fill: Deposit dielectric in gap → isolates adjacent gates.
6. Continue replacement metal gate (RMG) flow → each gate segment independent.
Timing of Cut
| Approach | When | Pros | Cons |
|---|---|---|---|
| Cut-first (before S/D epi) | During fin patterning | Simpler | Epi loading effects at cut boundary |
| Cut-last (after gate formation) | During RMG | Better isolation | More complex multi-step process |
| Cut-mid | After dummy gate, before RMG | Balanced | Moderate complexity |
EUV Cut Lithography
- Cut patterns are 2D (rectangles at specific locations) → more random than regular lines.
- ArF immersion: Struggles with cut pattern complexity → needs SADP assist.
- EUV: Single exposure for cut → simpler, better overlay to gate pattern.
- Cost trade-off: One more EUV mask layer vs. two ArF immersion + SADP layers.
Gate cut and single diffusion break are the patterning strategy that made unidirectional layout practical for advanced CMOS — by decoupling the creation of regular line patterns (simple for lithography) from the definition of individual circuit elements (complex 2D shapes), cut-based patterning achieves both lithographic simplicity and layout density, enabling the 10-15% area reduction per node that drives the continued economic scaling of semiconductor manufacturing.