Hybrid Bonding Interconnect
Hybrid bonding joins two wafers or dies by bonding copper pads and the surrounding dielectric at the same time, producing a metallurgical copper-to-copper connection with no solder, no underfill and no gap. Commercialised as direct bond interconnect (DBI), it is the interconnect that takes die-to-die pitch below the floor solder can reach.
Why solder stops
A micro-bump is a solder joint, and solder joints have a minimum viable volume. As pitch shrinks the joint must shrink, but the intermetallic compound that forms with the copper pad on reflow has a nearly fixed thickness, so it consumes a growing fraction of a shrinking joint until the connection is essentially all brittle IMC. Bridging risk rises at the same time, because molten solder must be confined to a shrinking footprint. The practical floor sits near 40 μm, with heroic processes reaching the mid-20s.
Hybrid bonding removes solder from the problem entirely, and pitch is then limited by lithographic overlay rather than metallurgy. Demonstrated pitches are below 1 μm; production is in the 3 to 10 μm range. Since interconnect density scales as $1/p^{2}$, this is a two-to-three order of magnitude increase in available connections.
The three surface requirements
The process succeeds or fails on surface preparation, and all three requirements are severe.
*Planarity.* The dielectric surfaces must contact intimately across the whole wafer, so CMP must deliver roughness well under a nanometre — the working specification is
across a 300 mm wafer. There is no reflow to accommodate topography; a surface that is not flat simply does not bond.
*Copper recess.* The copper pads must sit slightly below the dielectric plane, typically 2 to 10 nm, because bonding proceeds dielectric-first at room temperature and the copper is brought into contact afterwards by thermal expansion. Too little recess and copper contacts first, holding the dielectric surfaces apart and leaving voids. Too much and the copper cannot close the gap during anneal, leaving an open. The recess window is a CMP dishing control problem, and dishing depth in a damascene pad follows the Preston relation modified by pattern density,
so wide pads and low-density regions dish more. Dummy pad fill to equalise pattern density is therefore mandatory, exactly as it is for damascene copper.
*Cleanliness.* A single particle holds the surfaces apart over an area thousands of times its own diameter, producing a void that fails every connection inside it.
Bonding chemistry: SiO₂ and SiCN
Room-temperature bonding proceeds through hydrogen-bonded surface species that convert to covalent bonds on anneal. For silicon dioxide the condensation reaction is
and the water produced must diffuse away through the bond interface; trapped water is a classic void source. Silicon carbonitride has largely displaced plain oxide as the bonding dielectric because it reaches higher bond energy at lower anneal temperature, tolerates the copper recess process better, and simultaneously serves as a copper diffusion barrier — which plain oxide does not.
Copper closure during anneal is a combination of thermal expansion across the recess and grain-boundary diffusion across the now-contacting interface:
At 250 to 350 °C the pads expand into contact, then interdiffuse until the original interface disappears into a continuous grain structure. The finished joint is metallurgically indistinguishable from bulk copper, which is why hybrid-bonded interconnect carries far higher current density than a solder joint and exhibits essentially no electromigration at the interface.
| Micro-bump | Hybrid bond (DBI) | |
|---|---|---|
| Pitch floor | ~40 µm | <1 µm demonstrated |
| Joint material | solder + IMC | continuous Cu |
| Underfill | required | none |
| Electrical parasitics | bump L and C | near-zero |
| Thermal path | solder, poor | direct Cu, excellent |
| Process sensitivity | reflow profile | CMP, recess, particles |
Wafer-to-wafer versus die-to-wafer
W2W bonds two full wafers and achieves the finest pitch, because whole-wafer alignment is a lithographic problem. Its weakness is yield: dies are paired blind, so a good die can be bonded to a bad one, and compound yield falls as the product of the two. D2W places known-good dies onto a carrier wafer, preserving yield at the cost of coarser alignment and much lower throughput. The choice is economic — W2W suits high-yield, identical-die stacking such as memory; D2W suits expensive heterogeneous dies where discarding a good compute die is unacceptable.