Multi Bridge Channel FET MBCFET

# Multi-Bridge Channel FET (MBCFET): Architecture, Physics & Process Integration

The Multi-Bridge Channel Field-Effect Transistor (MBCFET) is Samsung Foundry's proprietary, high-volume manufacturing implementation of Gate-All-Around (GAA) nanosheet technology. First introduced commercially at the 3 nm node (3GAE / 3GAP / SF3) to succeed three-dimensional FinFETs, the MBCFET replaces conventional vertical silicon fins with multiple vertically stacked, horizontally oriented rectangular silicon ribbons—termed nano-bridges.

While early research into Gate-All-Around architectures focused on cylindrical silicon nanowires ($D \approx 5\,\text{nm}$), nanowires suffer from severely restricted total channel perimeter and consequently insufficient drive current ($I_{on} \propto \pi D$). The MBCFET overcomes this limitation by engineering wide, flat silicon bridges ($W_{bridge} \approx 20\text{ to }55\,\text{nm}$, $T_{bridge} \approx 5\,\text{nm}$), providing full four-sided electrostatic gate wrap-around while delivering up to $30\%\text{ to }40\%$ higher effective channel width ($W_{eff}$) per unit standard cell footprint compared to FinFETs. This architecture eliminates the rigid integer quantization constraints of FinFETs, enabling continuous, lithographically adjustable drive-strength tuning within a fixed standard cell height.

Transistor Architectural Evolution: Planar to MBCFET cross-sectional comparison of gate electrostatic wrap-around and effective channel perimeter 1. PLANAR MOSFET Top Gate (1-Sided) Inversion Layer Sub-Surface Leakage Gate Control: 1-Sided W_eff = W Severe DIBL < 28nm Historical Baseline 2. 3D FINFET Tri-Gate (3-Sided) Fin (~50nm) Gate Control: 3-Sided W_eff = 2H_fin + W_fin Quantized Fin Counts Production: 16nm–4nm 3. GAA NANOWIRE Gate Control: 4-Sided All-Around W_eff = N · π · D Tiny I_on (Narrow Area) Research Demonstrators 4. SAMSUNG MBCFET Bridge 3 (W=45nm) Bridge 2 (W=45nm) Bridge 1 (W=45nm) Gate Control: 4-Sided All-Around W_eff = N · (2W + 2T) +35% Drive vs. FinFET Continuous Width Scaling Samsung 3GAE / 3GAP / SF3

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## 1. Structural Architecture & Effective Channel Width Engineering

In modern standard cell library design, standard cell track height ($H_{cell}$) is fixed across the library (e.g., $5.0\,\text{T}$ or $4.5\,\text{T}$). In a FinFET technology, cell designers must accommodate a discrete number of vertical fins:

$$W_{eff,FinFET} = N_{fin} \cdot (2 H_{fin} + W_{fin})$$

Where $H_{fin} \approx 45\text{ to }50\,\text{nm}$ and $W_{fin} \approx 6\,\text{nm}$. A single-fin cell ($N_{fin} = 1$) delivers $W_{eff} \approx 100\,\text{nm}$, while a double-fin cell ($N_{fin} = 2$) jumps directly to $W_{eff} \approx 200\,\text{nm}$. Designers cannot create intermediate drive strengths ($1.3\times$ or $1.6\times$) without expanding cell height or stacking multiple library cells in parallel.

### 1.1 The MBCFET Continuous Width Formulation
In Samsung's Multi-Bridge Channel FET, each active transistor consists of $N_{bridge}$ horizontally stacked silicon ribbons (typically $N_{bridge} = 3\text{ or }4$). The total effective channel width wraps around all four boundaries:

$$W_{eff,MBCFET} = N_{bridge} \cdot \big( 2 W_{bridge} + 2 T_{bridge} \big)$$

Where:
- $W_{bridge}$ is the lithographically defined horizontal bridge width, continuously variable between $15\,\text{nm}$ and $55\,\text{nm}$.
- $T_{bridge} \approx 5\,\text{nm}$ is the epitaxially defined bridge thickness.

+----------------------------------------------------------------------------------------------------+
|                               MBCFET EFFECTIVE CHANNEL WIDTH (N_bridge = 3, T = 5 nm)              |
+---------------------+-------------------+---------------------+------------------------------------+
| TARGET CELL CLASS   | BRIDGE WIDTH (W)  | W_eff PER TRANSISTOR| FINFET EQUIVALENT / COMPARISON     |
+---------------------+-------------------+---------------------+------------------------------------+
| Ultra-Low Power     | 20 nm             | 150 nm              | 1.5× of 1-Fin FinFET (Fine step)   |
+---------------------+-------------------+---------------------+------------------------------------+
| Standard Logic      | 35 nm             | 240 nm              | 1.25× of 2-Fin FinFET (Matched T)  |
+---------------------+-------------------+---------------------+------------------------------------+
| High Performance    | 50 nm             | 330 nm              | 1.72× of 2-Fin FinFET (+40% drive) |
+---------------------+-------------------+---------------------+------------------------------------+

Because bridge width is modulated purely in the front-end EUV lithography mask layout, standard cell designers can mix narrow-bridge low-leakage cells (e.g., in high-density SRAM bitcells or idle control logic) with wide-bridge high-current cells (in critical timing clock buffers and arithmetic units) within the exact same row height and poly pitch.

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## 2. Quantitative Modeling: PPA Scaling & Crystal Plane Mobility

Samsung MBCFET Performance, Power & Area (PPA) Scaling 3nm MBCFET (3GAP/SF3) vs. 4nm FinFET frequency-power curves and crystallographic mobility OPERATING FREQUENCY vs. ACTIVE POWER 4.0 GHz 3.5 GHz 3.0 GHz 2.5 GHz 2.0 GHz 0 200 400 600 800 4nm FinFET 3nm MBCFET (3GAP) +22% Speed @ Same Power -45% Power @ 3.3 GHz Normalized Active Core Power (mW) → CRYSTAL PLANES & QUANTUM VOLUME INVERSION 4-Sided High-k Metal Gate (HKMG) Top Surface: {100} Plane (High μ_e ≈ 650 cm²/V·s) Bottom Surface: {100} Plane (High μ_e ≈ 650 cm²/V·s) {110} Sidewall {110} Sidewall Quantum Inversion Centroid (Zero Surface Roughness Loss) • Dominant {100} Conduction: Wide W_bridge ensures >85% of channel current travels across low-effective-mass {100} surfaces, boosting NMOS. • Quantum Volume Inversion (T_bridge ≤ 5 nm): Inversion charge peaks at the geometric bridge center, eliminating surface roughness scattering and raising μ_eff. Physical Transport Mechanisms →

### 2.1 Surface Crystallography & Carrier Mobility Physics
In silicon CMOS, electron and hole mobilities exhibit strong anisotropy across crystallographic planes:
- $\{100\}$ Plane: Conduction along $\langle 110 \rangle$ yields peak electron mobility ($\mu_{e} \approx 650\,\text{cm}^2/\text{V}\cdot\text{s}$), but low hole mobility ($\mu_{h} \approx 130\,\text{cm}^2/\text{V}\cdot\text{s}$).
- $\{110\}$ Plane: Conduction along $\langle 110 \rangle$ yields superior hole mobility ($\mu_{h} \approx 220\,\text{cm}^2/\text{V}\cdot\text{s}$), but heavily degraded electron mobility ($\mu_{e} \approx 350\,\text{cm}^2/\text{V}\cdot\text{s}$).

In a 3D FinFET, the vertical sidewalls dominate the conduction perimeter ($2H_{fin} \approx 100\,\text{nm}$ vs. $W_{fin} \approx 6\,\text{nm}$). FinFET sidewalls are oriented along $\{110\}$ planes on standard $(001)$ wafers, favoring PMOS but severely compromising NMOS electron mobility.

In contrast, the MBCFET has wide horizontal bridges ($W_{bridge} \gg T_{bridge}$, aspect ratio $W/T \approx 5\text{ to }10$). The weighted effective mobility is given by:

$$\mu_{eff} = \frac{2 W_{bridge} \cdot \mu_{\{100\}} + 2 T_{bridge} \cdot \mu_{\{110\}}}{2 W_{bridge} + 2 T_{bridge}} = \frac{W_{bridge} \mu_{\{100\}} + T_{bridge} \mu_{\{110\}}}{W_{bridge} + T_{bridge}}$$

For an NMOS bridge with $W_{bridge} = 40\,\text{nm}$ and $T_{bridge} = 5\,\text{nm}$:

$$\mu_{eff,NMOS} = \frac{(40 \cdot 650) + (5 \cdot 350)}{45} = \frac{26000 + 1750}{45} \approx 616.7\,\text{cm}^2/\text{V}\cdot\text{s}$$

This represents an over $60\%$ electron mobility advantage over FinFET vertical $\{110\}$ sidewalls. For PMOS, where $\{100\}$ mobility is lower, high uniaxial compressive strain ($\sigma_{xx} \approx -2.5\,\text{GPa}$) is introduced via heavily boron-doped silicon-germanium ($\text{Si}_{0.65}\text{Ge}_{0.35}\text{:B}$) epitaxial source/drain stressors, splitting the heavy-hole and light-hole valence sub-bands and restoring symmetric drive current between NMOS and PMOS ($I_{on,P} / I_{on,N} \approx 0.90$).

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## 3. MBCFET Process Integration Sequence

Samsung's MBCFET integration flow consists of several specialized front-end modules:

+----------------------------------------------------------------------------------------------------+
|                                    MBCFET UNIT PROCESS SEQUENCE                                    |
+----------------------+-------------------------------------+---------------------------------------+
| PROCESS MODULE       | KEY PARAMETERS & TOOLS              | PHYSICAL FUNCTION                     |
+----------------------+-------------------------------------+---------------------------------------+
| 1. Superlattice Epi  | RP-CVD @ 600°C; Si/Si₀.₇Ge₀.₃;      | Alternating lattice-matched channel   |
|                      | 3-4 sheet stack; t_sac = 10 nm      | and sacrificial release layers        |
+----------------------+-------------------------------------+---------------------------------------+
| 2. Fin & Bridge Mask | EUV Litho (0.33 NA, λ = 13.5 nm);   | Continuously modulates bridge width   |
|                      | Cryogenic RIE (-40°C to -80°C)      | W_bridge without fin pitch limits     |
+----------------------+-------------------------------------+---------------------------------------+
| 3. Inner Spacer Cav  | Vapor-phase selective lateral etch; | Creates self-aligned dielectric recess|
|                      | Low-k SiOCN ALD fill + etch-back    | to decouple gate from S/D epitaxy     |
+----------------------+-------------------------------------+---------------------------------------+
| 4. Selective S/D Epi | NMOS: Si:P (P > 3×10²⁰ cm⁻³);       | In-situ faceted stressors; delivers   |
|                      | PMOS: SiGe:B (Ge 35%, B > 10²¹ cm⁻³)| low contact resistance R_c < 1.5×10⁻⁹ |
+----------------------+-------------------------------------+---------------------------------------+
| 5. Bridge Release    | Gas-phase thermal vapor HCl;        | Strips SiGe with > 250:1 selectivity; |
|                      | Zero-meniscus sublimation clean     | leaves suspended crystalline bridges  |
+----------------------+-------------------------------------+---------------------------------------+
| 6. Replacement HKMG  | ALD HfO₂ (k = 22, EOT = 0.8 nm);    | 4-sided electrostatic wrap;           |
|                      | Dual workfunction metals + W/Ru fill| sets multi-Vt (e.g., SLVT, LVT, SVT)  |
+----------------------+-------------------------------------+---------------------------------------+

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## 4. Foundry Implementation: Samsung 3GAE, 3GAP, and SF3 Nodes

Samsung Foundry became the first manufacturer in semiconductor history to enter high-volume manufacturing of Gate-All-Around technology using MBCFET at the 3 nm node:

1. 3GAE (3nm Gate-All-Around Early, 2022):
- First-generation commercial MBCFET node.
- Demonstrated up to $45\%$ reduction in power consumption, $23\%$ performance improvement, and $16\%$ reduction in silicon area compared to Samsung 5 nm FinFET.
2. 3GAP / SF3 (3nm Gate-All-Around Production / SF3, 2024–2025):
- Optimized second-generation MBCFET featuring refined inner spacer low-k dielectrics ($\kappa \le 4.2$) and thinner interfacial oxide layers.
- Reduced operating voltage ($V_{DD} = 0.68\,\text{V}$) with enhanced drive current ($I_{on} > 1.2\,\text{mA}/\mu\text{m}$).
3. SF2 (2nm Node Transition):
- Incorporates Backside Power Delivery Networks (BSPDN) and Bottom Dielectric Isolation (BDI) into the MBCFET channel stack, targeting high-performance computing (HPC) and mobile AI processors.

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## 5. Technology Comparison: FinFET, Nanowire GAA, and MBCFET

+----------------------------------------------------------------------------------------------------+
|                               COMPARATIVE MATRIX OF 3D/GAA TRANSISTORS                             |
+----------------------+---------------------+-----------------------+-------------------------------+
| PARAMETER            | 5nm / 4nm FINFET    | GAA NANOWIRE          | SAMSUNG 3nm MBCFET (SF3)      |
+----------------------+---------------------+-----------------------+-------------------------------+
| Channel Geometry     | Vertical 3D fin     | Cylindrical wire      | Wide rectangular nano-bridge  |
|                      | H ~45 nm, W ~6 nm   | Diameter D ~5 nm      | Width 20–55 nm, Thick 5 nm    |
+----------------------+---------------------+-----------------------+-------------------------------+
| Gate Topology        | 3-sided tri-gate    | 4-sided cylindrical   | 4-sided full planar wrap      |
|                      | wrap-around         | all-around wrap       | around rectangular bridges    |
+----------------------+---------------------+-----------------------+-------------------------------+
| Effective Channel    | Quantized           | Extremely small       | High and continuously variable|
| Width (W_eff)        | W_eff = N(2H + W)   | W_eff = N · π · D     | W_eff = N · (2W + 2T)         |
+----------------------+---------------------+-----------------------+-------------------------------+
| Drive Current (I_on) | 0.8–1.0 mA/μm       | 0.3–0.5 mA/μm         | 1.1–1.3 mA/μm                 |
|                      | (Fin pitch limited) | (Insufficient current)| (+30–40% vs. FinFET)          |
+----------------------+---------------------+-----------------------+-------------------------------+
| Subthreshold Swing   | 68 to 74 mV/dec     | 62 to 64 mV/dec       | 63 to 65 mV/dec               |
| (SS @ short Lg)      | (Drain leakage loss)| (Near ideal limit)    | (Near ideal limit)            |
+----------------------+---------------------+-----------------------+-------------------------------+
| Dynamic Power (P_dyn)| Baseline (1.0×)     | 0.75×                 | 0.55× to 0.65× (-35 to -45%)  |
+----------------------+---------------------+-----------------------+-------------------------------+
| Commercial Status    | High Volume Mass Pro| Research / Niche      | High Volume Mass Production   |
|                      | (Mature leading edge| Demonstrators Only    | (Samsung 3GAE / SF3 / SF2)    |
+----------------------+---------------------+-----------------------+-------------------------------+

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