Power Intent UPF
Power Intent (UPF/IEEE 1801) is the standardized specification format that describes the power management architecture of a chip — defining power domains, supply nets, isolation cells, retention registers, level shifters, and power switching sequences in a technology-independent way that enables EDA tools to implement, verify, and simulate complex multi-voltage, power-gated designs.
Why Power Intent?
- Modern SoCs have dozens of power domains — each can be independently powered, voltage-scaled, or shut off.
- RTL code describes function but NOT power management behavior.
- UPF is a separate specification that overlays power behavior onto the RTL design.
- Without UPF: Tools don't know which cells need isolation, which need retention, where level shifters go.
UPF Key Concepts
| Concept | UPF Command | Purpose |
|---|---|---|
| Power Domain | `create_power_domain` | Group of logic sharing same power supply |
| Supply Net | `create_supply_net` | Named power/ground wire |
| Supply Port | `create_supply_port` | Connection point for supply |
| Power Switch | `create_power_switch` | MTCMOS header/footer for power gating |
| Isolation | `set_isolation` | Clamp outputs when domain is off |
| Retention | `set_retention` | Save/restore register state across power-off |
| Level Shifter | `set_level_shifter` | Convert signals between voltage domains |
Power Domain States
| State | Supply | Logic | Outputs |
|---|---|---|---|
| ON (active) | Vdd nominal | Functional | Driven by logic |
| OFF (power-gated) | Vdd = 0 | Undefined | Clamped by isolation cells |
| RETENTION | Vdd = 0, Vret = on | State saved in balloon latches | Clamped |
| LOW VOLTAGE | Vdd reduced (DVFS) | Functional (slower) | Driven |
UPF Example
create_power_domain PD_GPU -elements {gpu_top}
create_supply_net VDD_GPU -domain PD_GPU
create_power_switch SW_GPU -domain PD_GPU \
-input_supply_port {vin VDD_ALWAYS} \
-output_supply_port {vout VDD_GPU}
set_isolation iso_gpu -domain PD_GPU \
-isolation_power_net VDD_ALWAYS \
-clamp_value 0
set_retention ret_gpu -domain PD_GPU \
-save_signal {gpu_save posedge} \
-restore_signal {gpu_restore posedge}UPF in Design Flow
1. Architecture: Architect defines power domains and states.
2. UPF specification: Written alongside RTL.
3. Simulation: UPF-aware simulator (VCS, Xcelium) models power states — verifies isolation/retention behavior.
4. Synthesis: DC reads UPF → inserts isolation cells, level shifters, retention flops.
5. P&R: Implements power switches, supply routing per UPF.
6. Signoff: Verify all UPF rules satisfied in final layout.
Power intent specification is essential for modern SoC design — without UPF, it would be impossible to systematically design, implement, and verify the complex multi-domain power management architectures that enable smartphone processors to deliver high performance while lasting a full day on battery.