Power Intent UPF CPF

Power Intent Specification (UPF/CPF) is the formal design methodology that captures a chip's power management architecture — including voltage domains, power states, isolation strategies, retention policies, and level shifting requirements — in a standardized format (IEEE 1801 UPF or Cadence CPF) that is used by all EDA tools from RTL simulation through physical implementation to ensure correct multi-voltage, power-gating, and dynamic voltage-frequency scaling behavior.

Why Power Intent Is Separate from RTL

Power management cross-cuts the entire design. A single signal may traverse three voltage domains, requiring level shifters at each crossing. A power domain may have four operating states (full-on, retention, clock-gated, power-off). Embedding these details in RTL would make the code unreadable and unverifiable. UPF captures power intent declaratively, orthogonal to functional RTL.

Key UPF Concepts

• Supply Network: `create_supply_net`, `create_supply_set`, `connect_supply_net` define the power and ground rails feeding each domain. Multiple supply sets model multi-rail designs (e.g., core at 0.75V, I/O at 1.8V, SRAM at 0.8V).
• Power Domain: `create_power_domain` groups design elements sharing a common power supply. The top-level domain is always on; child domains can be switched.
• Power State Table: `add_power_state` defines legal combinations of supply voltages across all domains. The PST enumerates states like RUN (all on), STANDBY (cores off, always-on domain active), SLEEP (only RTC domain powered).
• Isolation Strategy: `set_isolation` specifies that outputs from a powered-off domain must be clamped (to 0, 1, or a latch value) to prevent floating signals from corrupting always-on logic. Isolation cells are inserted at domain boundaries.
• Retention Strategy: `set_retention` specifies which registers must retain their state when the domain is powered off. Retention flip-flops (balloon latches or separate supply cells) save register contents to the always-on supply during power-down.
• Level Shifters: `set_level_shifter` specifies voltage translation at crossings between domains operating at different voltages. Required for both signal integrity and reliability.

Verification Flow

• UPF-Aware Simulation: Tools like Synopsys VCS and Cadence Xcelium simulate power state transitions, verifying isolation, retention save/restore, and level shifter insertion correctness at RTL.
• Static Verification: Cadence Conformal Low Power and Synopsys MVRC check UPF consistency, completeness (all crossings covered), and correctness against design rules.
• Physical Verification: Tools verify that physical implementation matches UPF intent — correct cells inserted, supply connections correct, power switches properly sized.

Power Intent Specification is the contract between the architect's power vision and the implementation tools — ensuring that a chip's multi-voltage, power-gating, and retention behavior is correct by construction across the entire design flow from RTL to GDSII.